diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config index daef32c4e9c6..00decc6710b4 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config @@ -182,7 +182,7 @@ CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y -CONFIG_RT_VER_NUM=0x50300 +CONFIG_RT_VER_NUM=0x50400 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -468,6 +468,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ABUP_FOTA is not set # CONFIG_PKG_USING_LIBCURL2RTT is not set # CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_ERPC is not set # CONFIG_PKG_USING_AGILE_TELNET is not set # CONFIG_PKG_USING_NMEALIB is not set # CONFIG_PKG_USING_PDULIB is not set @@ -554,6 +555,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_LVGL is not set # CONFIG_PKG_USING_LV_MUSIC_DEMO is not set # CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# GD32EmbeddedUI demos require LVGL v8.3.11 +# # end of LVGL: powerful and easy-to-use embedded GUI library # @@ -583,12 +588,15 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_3GPP_AMRNB is not set +# CONFIG_PKG_USING_LITETYPE is not set # end of multimedia packages # # tools packages # # CONFIG_PKG_USING_VECTOR is not set +# CONFIG_PKG_USING_SORCH is not set +# CONFIG_PKG_USING_DICT is not set # CONFIG_PKG_USING_CMBACKTRACE is not set # CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set @@ -640,6 +648,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UORB is not set # CONFIG_PKG_USING_RT_TUNNEL is not set # CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# CONFIG_PKG_USING_FEE is not set +# CONFIG_PKG_USING_MRAMTRACE is not set # end of tools packages # @@ -735,6 +745,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_HEARTBEAT is not set # CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set # CONFIG_PKG_USING_CHERRYECAT is not set +# CONFIG_PKG_USING_EVENT_LOOP is not set +# CONFIG_PKG_USING_THREAD_MANAGER is not set # end of system packages # @@ -786,6 +798,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set # CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set # CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32N657xx_FSBL is not set # end of STM32 HAL & SDK Drivers # @@ -818,7 +833,21 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set -# CONFIG_PKG_USING_MM32 is not set + +# +# MM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_MM32F103XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F3270X_CMSIS is not set +# CONFIG_PKG_USING_MM32F5260X_CMSIS is not set +# CONFIG_PKG_USING_MM32L0XX_CMSIS is not set +# CONFIG_PKG_USING_MM32L3XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F103XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F3270X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F5260X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L0XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L3XX_HAL_DRIVER is not set +# end of MM32 HAL & SDK Drivers # # WCH HAL & SDK Drivers @@ -883,9 +912,7 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" # # NUVOTON Drivers # -# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set # CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set -# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set # end of NUVOTON Drivers # @@ -903,6 +930,12 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" # CONFIG_PKG_USING_HPM_SDK is not set # end of HPMicro SDK +# +# FM33 Drivers +# +# CONFIG_PKG_USING_FM33LG0XX_FL_LIBRARY is not set +# end of FM33 Drivers + # # FT32 HAL & SDK Drivers # @@ -911,6 +944,23 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" # CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set # CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set # end of FT32 HAL & SDK Drivers + +# +# NOVOSNS Drivers +# +# CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER is not set +# end of NOVOSNS Drivers + +# +# N32 Drivers +# +# CONFIG_PKG_USING_N32H7XX_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H7XX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_CMSIS_DRIVER is not set +# end of N32 Drivers # end of HAL & SDK Drivers # @@ -990,6 +1040,7 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" # CONFIG_PKG_USING_QMI8658 is not set # CONFIG_PKG_USING_ICM20948 is not set # CONFIG_PKG_USING_SCD4X is not set +# CONFIG_PKG_USING_BMI270 is not set # end of sensors drivers # @@ -1044,6 +1095,7 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" # CONFIG_PKG_USING_WK2124 is not set # CONFIG_PKG_USING_LY68L6400 is not set # CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_CH390 is not set # CONFIG_PKG_USING_SSD1306 is not set # CONFIG_PKG_USING_QKEY is not set # CONFIG_PKG_USING_RS485 is not set @@ -1091,8 +1143,10 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" # CONFIG_PKG_USING_ISOTP_C is not set # CONFIG_PKG_USING_IKUNLED is not set # CONFIG_PKG_USING_INS5T8025 is not set +# CONFIG_PKG_USING_IRUART is not set # CONFIG_PKG_USING_ST7305 is not set # CONFIG_PKG_USING_TM1668 is not set +# CONFIG_PKG_USING_TCA9548A is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1110,6 +1164,9 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" # CONFIG_PKG_USING_NAXOS is not set # CONFIG_PKG_USING_R_TINYMAIX is not set # CONFIG_PKG_USING_LLMCHAT is not set +# CONFIG_PKG_USING_LIME_TM is not set +# CONFIG_PKG_USING_AIFES is not set +# CONFIG_PKG_USING_AGENT is not set # end of AI packages # @@ -1169,6 +1226,8 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_CANOPENNODE is not set +# CONFIG_PKG_USING_LELY is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_MINIZIP is not set # CONFIG_PKG_USING_HEATSHRINK is not set @@ -1194,6 +1253,8 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" # CONFIG_PKG_USING_QPARAM is not set # CONFIG_PKG_USING_CorevMCU_CLI is not set # CONFIG_PKG_USING_DRMP is not set +# CONFIG_PKG_USING_AUTOGEN_PARAMETER_MANAGER is not set +# CONFIG_PKG_USING_SIMULATED_SENSOR is not set # end of miscellaneous packages # @@ -1488,6 +1549,7 @@ CONFIG_BSP_LPUART1_TX_DMA_CHANNEL=1 # Board extended module Drivers # # CONFIG_BSP_LINKER_SCRIPT_RAM is not set +# CONFIG_BSP_LINKER_SCRIPT_RAM_INDUSTRY is not set CONFIG_BSP_LINKER_SCRIPT_FLEXSPI_NOR=y # CONFIG_BSP_LINKER_SCRIPT_FLEXSPI_NOR_HYPERRAM is not set # end of Hardware Drivers Config diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/multicore_thread.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/multicore_thread.c index 9cdd88d68c62..5493860b3a2c 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/multicore_thread.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/multicore_thread.c @@ -83,7 +83,7 @@ static bool error_occurred = false; static volatile uint32_t remote_addr = 0U; #endif /* BSP_USE_MULTICORE_RPMSG_LITE */ -#ifdef BSP_USE_MULTICORE_KICK_OFF +#if defined(BSP_USE_MULTICORE_KICK_OFF) && defined(BSP_USE_MULTICORE_RPMSG_LITE) static volatile uint16_t RPMsgRemoteReadyEventData = 0U; #endif @@ -92,11 +92,13 @@ static volatile uint16_t RPMsgRemoteReadyEventData = 0U; ******************************************************************************/ #ifdef BSP_USE_MULTICORE_KICK_OFF +#ifdef BSP_USE_MULTICORE_RPMSG_LITE static void RPMsgRemoteReadyEventHandler(mcmgr_core_t coreNum, uint16_t eventData, void *context) { uint16_t *data = (uint16_t *)context; *data = eventData; } +#endif static rt_err_t multicore_kickoff_init(void) { diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig index a8e23399de66..70a32c07b8c3 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig @@ -815,6 +815,15 @@ choice help Link the image to run entirely from internal SRAM. + config BSP_LINKER_SCRIPT_RAM_INDUSTRY + bool "RAM - Industrial Ethernet (256KB TCM + 128KB OCRAM2 + 32KB shared memory)" + help + Link the image to run from 256KB TCM for industrial Ethernet + development. CM33 uses 128KB OCRAM2 exclusively and shares 32KB + OCRAM2 with CM7. The GCC linker script (.ld), the ARMCLANG + scatter file (.scf) and the IAR linker configuration file (.icf) + are provided. + config BSP_LINKER_SCRIPT_FLEXSPI_NOR bool "FlexSPI NOR Flash (XIP from external NOR flash)" help diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c index 70b7b41b6b53..f56b6b289649 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c @@ -1498,8 +1498,8 @@ void PHY_Reset(void) void rt_hw_board_init() { extern void BOARD_InitPeripherals(void); - BOARD_CommonSetting(); BOARD_ConfigMPU(); + BOARD_CommonSetting(); BOARD_InitBootPins(); BOARD_BootClockRUN(); // BOARD_InitPeripherals(); diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor.icf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor.icf index 4b08ecca3c88..88f2bb3cfad0 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor.icf +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor.icf @@ -1,183 +1,183 @@ -/* -** ################################################################### -** Processors: MIMXRT1189CVM8B_cm33 -** MIMXRT1189CVM8C_cm33 -** MIMXRT1189XVM8B_cm33 -** MIMXRT1189XVM8C_cm33 -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: IMXRT1180RM, Rev 5, 01/2024 -** Version: rev. 2.0, 2024-01-18 -** Build: b250310 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2025 NXP -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -/* Board memory map */ - -define symbol m_code_tcm_start = 0x0FFE0000; -define symbol m_code_tcm_size = 0x00020000; - -define symbol m_system_tcm_start = 0x20000000; -define symbol m_system_tcm_size = 0x00020000; - -define symbol m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */ -define symbol m_ocram1_size = 0x0007C000; - -define symbol m_ocram2_start = 0x20500000; -define symbol m_ocram2_size = 0x00040000; - -/* CM33 use last 2M bytes space of sdram and hyperram for dual image framework */ -define symbol m_sdram_start = isdefinedsymbol(__dual_image__) ? 0x81E00000 : 0x80000000; -define symbol m_sdram_size = isdefinedsymbol(__dual_image__) ? 0x00200000 : 0x02000000; -define symbol m_hyperram_start = isdefinedsymbol(__dual_image__) ? 0x04600000 : 0x04000000; -define symbol m_hyperram_size = isdefinedsymbol(__dual_image__) ? 0x00200000 : 0x00800000; -define symbol m_flash_start = 0x28000000; -define symbol m_flash_size = 0x00800000; - -define symbol m_core1_image_maximum_size = 0x00040000; - -/* General definition */ -define symbol m_fcb_offset = 0x400; -define symbol m_fcb_size = 0x200; -define symbol m_fcb_start = m_flash_start + m_fcb_offset; -define symbol m_fcb_end = m_fcb_start + m_fcb_size - 1; - -define symbol m_xmcd_offset = 0x800; -define symbol m_xmcd_size = 0x400; -define symbol m_xmcd_start = m_flash_start + m_xmcd_offset; -define symbol m_xmcd_end = m_xmcd_start + m_xmcd_size - 1; - -define symbol m_container_offset = 0x1000; -define symbol m_container_size = 0x2000; -define symbol m_container_start = m_flash_start + m_container_offset; -define symbol m_container_end = m_container_start + m_container_size - 1; - -define symbol app_image_offset = 0x0000B000; -define symbol vector_table_size = 0x00000400; -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x01000; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x08000; -} - -define symbol m_qacode_start = m_code_tcm_start + (isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0); -define symbol m_qacode_end = m_code_tcm_start + m_code_tcm_size - 1; -define symbol m_qadata_start = m_system_tcm_start; -define symbol m_qadata_end = m_system_tcm_start + m_system_tcm_size - 1; -define symbol m_ram_vector_table_start = m_code_tcm_start; - -/* Target specific definition, code & data allocation */ -define symbol m_code_size = m_flash_size - app_image_offset; -define symbol m_data_size = m_system_tcm_size; -define symbol m_ncache_size = isdefinedsymbol(__multicore__) ? 0x20000 : 0x40000; /* m_ncache_size must be 2^N */ -define symbol m_shmem_size = m_ocram2_size; /* m_shmem_size must be 2^N */ - -define symbol m_ocram1_size_for_cm7 = isdefinedsymbol(__multicore__) ? 0x40000 : 0; - -define symbol m_ram_vector_table_size = isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0; - -define symbol m_text_start = m_flash_start + app_image_offset; -define symbol m_text_end = m_text_start + m_code_size - 1; -define symbol m_interrupts_start = m_text_start; - -define symbol m_data_start = m_system_tcm_start; -define symbol m_data_end = m_data_start + m_data_size - 1; - -define symbol m_ncache_start = m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7 - m_ncache_size; -define symbol m_ncache_end = m_ncache_start + m_ncache_size - 1; - -define symbol m_heap_start = m_ocram1_start; -define symbol m_heap_end = m_ncache_start - 1; - -if (isdefinedsymbol(__use_shmem__)) { - define symbol m_rpmsg_sh_mem_start = m_ocram2_start; - define symbol m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; -} - -/* Region definition */ -define memory mem with size = 4G; -define region FCB_region = mem:[from m_fcb_start to m_fcb_end]; -define region XMCD_region = mem:[from m_xmcd_start to m_xmcd_end]; -define region CONTAINER_region = mem:[from m_container_start to m_container_end]; -define region TEXT_region = mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; -define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; -define region HEAP_region = mem:[from m_heap_start to m_heap_end]; -define region QACODE_region = mem:[from m_qacode_start to m_qacode_end]; -define region QADATA_region = mem:[from m_qadata_start to m_qadata_end]; -if (isdefinedsymbol(__use_shmem__)) { - define region rpmsg_sh_mem_region = mem:[from m_rpmsg_sh_mem_start to m_rpmsg_sh_mem_end]; -} - -/* Exported symbol definition */ -define exported symbol __VECTOR_TABLE = m_interrupts_start; -define exported symbol __VECTOR_RAM = m_ram_vector_table_start; -define exported symbol __RAM_VECTOR_TABLE_SIZE = m_ram_vector_table_size; -define exported symbol __NCACHE_REGION_START = m_ncache_start; -define exported symbol __NCACHE_REGION_SIZE = m_ncache_end - m_ncache_start + 1; -define exported symbol __CONTAINER_IMG_OFFSET = start(TEXT_region) - start(CONTAINER_region); -define exported symbol __CONTAINER_IMG_LOAD_ADDR = start(TEXT_region); -define exported symbol __CONTAINER_IMG_ENTRY_ADDR = start(TEXT_region); -if (isdefinedsymbol(__use_shmem__)) { - define exported symbol rpmsg_sh_mem_start = m_rpmsg_sh_mem_start; - define exported symbol rpmsg_sh_mem_end = m_rpmsg_sh_mem_end; - define exported symbol __RPMSG_SH_MEM_START = m_rpmsg_sh_mem_start; - define exported symbol __RPMSG_SH_MEM_SIZE = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1; -} - -/* Block definition */ -define block RW { readwrite }; -define block ZI { zi }; -define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; -define block QACCESS_CODE { section CodeQuickAccess }; -define block QACCESS_DATA { section DataQuickAccess }; -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block CORE1_IMAGE_BLOCK with alignment = 16, maximum size = m_core1_image_maximum_size { section __core1_image }; - -define block RO with fixed order { readonly section .intvec, readonly, block CORE1_IMAGE_BLOCK }; - -initialize by copy { readwrite, section .textrw, section DataQuickAccess, section CodeQuickAccess, ro code object fsl_flexspi.o, ro code object drv_flexspi_nor_flash.o, ro code object drv_flexspi.o }; -do not initialize { section .noinit }; -if (isdefinedsymbol(__use_shmem__)) { - do not initialize { section rpmsg_sh_mem_section }; -} - -keep{ section .boot_hdr.conf, section .boot_hdr.xmcd_data, section .boot_hdr.container }; - -place in FCB_region { section .boot_hdr.conf }; -place in XMCD_region { section .boot_hdr.xmcd_data }; -place in CONTAINER_region { section .boot_hdr.container }; -place in TEXT_region { first block RO }; -place in QACODE_region { section .textrw, block QACCESS_CODE }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { block QACCESS_DATA }; -place in NCACHE_region { block NCACHE_VAR }; -place in CSTACK_region { block CSTACK }; -if (isdefinedsymbol(__heap_noncacheable__)) { - place in NCACHE_region { last block HEAP }; -} else { - place in HEAP_region { last block HEAP }; -} -if (isdefinedsymbol(__use_shmem__)) { - place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; -} +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm33 +** MIMXRT1189CVM8C_cm33 +** MIMXRT1189XVM8B_cm33 +** MIMXRT1189XVM8C_cm33 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Board memory map */ + +define symbol m_code_tcm_start = 0x0FFE0000; +define symbol m_code_tcm_size = 0x00020000; + +define symbol m_system_tcm_start = 0x20000000; +define symbol m_system_tcm_size = 0x00020000; + +define symbol m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */ +define symbol m_ocram1_size = 0x0007C000; + +define symbol m_ocram2_start = 0x20500000; +define symbol m_ocram2_size = 0x00040000; + +/* CM33 use last 2M bytes space of sdram and hyperram for dual image framework */ +define symbol m_sdram_start = isdefinedsymbol(__dual_image__) ? 0x81E00000 : 0x80000000; +define symbol m_sdram_size = isdefinedsymbol(__dual_image__) ? 0x00200000 : 0x02000000; +define symbol m_hyperram_start = isdefinedsymbol(__dual_image__) ? 0x04600000 : 0x04000000; +define symbol m_hyperram_size = isdefinedsymbol(__dual_image__) ? 0x00200000 : 0x00800000; +define symbol m_flash_start = 0x28000000; +define symbol m_flash_size = 0x00800000; + +define symbol m_core1_image_maximum_size = 0x00040000; + +/* General definition */ +define symbol m_fcb_offset = 0x400; +define symbol m_fcb_size = 0x200; +define symbol m_fcb_start = m_flash_start + m_fcb_offset; +define symbol m_fcb_end = m_fcb_start + m_fcb_size - 1; + +define symbol m_xmcd_offset = 0x800; +define symbol m_xmcd_size = 0x400; +define symbol m_xmcd_start = m_flash_start + m_xmcd_offset; +define symbol m_xmcd_end = m_xmcd_start + m_xmcd_size - 1; + +define symbol m_container_offset = 0x1000; +define symbol m_container_size = 0x2000; +define symbol m_container_start = m_flash_start + m_container_offset; +define symbol m_container_end = m_container_start + m_container_size - 1; + +define symbol app_image_offset = 0x0000B000; +define symbol vector_table_size = 0x00000400; +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x01000; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x08000; +} + +define symbol m_qacode_start = m_code_tcm_start + (isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0); +define symbol m_qacode_end = m_code_tcm_start + m_code_tcm_size - 1; +define symbol m_qadata_start = m_system_tcm_start; +define symbol m_qadata_end = m_system_tcm_start + m_system_tcm_size - 1; +define symbol m_ram_vector_table_start = m_code_tcm_start; + +/* Target specific definition, code & data allocation */ +define symbol m_code_size = m_flash_size - app_image_offset; +define symbol m_data_size = m_system_tcm_size; +define symbol m_ncache_size = isdefinedsymbol(__multicore__) ? 0x20000 : 0x40000; /* m_ncache_size must be 2^N */ +define symbol m_shmem_size = m_ocram2_size; /* m_shmem_size must be 2^N */ + +define symbol m_ocram1_size_for_cm7 = isdefinedsymbol(__multicore__) ? 0x40000 : 0; + +define symbol m_ram_vector_table_size = isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0; + +define symbol m_text_start = m_flash_start + app_image_offset; +define symbol m_text_end = m_text_start + m_code_size - 1; +define symbol m_interrupts_start = m_text_start; + +define symbol m_data_start = m_system_tcm_start; +define symbol m_data_end = m_data_start + m_data_size - 1; + +define symbol m_ncache_start = m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7 - m_ncache_size; +define symbol m_ncache_end = m_ncache_start + m_ncache_size - 1; + +define symbol m_heap_start = m_ocram1_start; +define symbol m_heap_end = m_ncache_start - 1; + +if (isdefinedsymbol(__use_shmem__)) { + define symbol m_rpmsg_sh_mem_start = m_ocram2_start; + define symbol m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; +} + +/* Region definition */ +define memory mem with size = 4G; +define region FCB_region = mem:[from m_fcb_start to m_fcb_end]; +define region XMCD_region = mem:[from m_xmcd_start to m_xmcd_end]; +define region CONTAINER_region = mem:[from m_container_start to m_container_end]; +define region TEXT_region = mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; +define region HEAP_region = mem:[from m_heap_start to m_heap_end]; +define region QACODE_region = mem:[from m_qacode_start to m_qacode_end]; +define region QADATA_region = mem:[from m_qadata_start to m_qadata_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from m_rpmsg_sh_mem_start to m_rpmsg_sh_mem_end]; +} + +/* Exported symbol definition */ +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_ram_vector_table_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = m_ram_vector_table_size; +define exported symbol __NCACHE_REGION_START = m_ncache_start; +define exported symbol __NCACHE_REGION_SIZE = m_ncache_end - m_ncache_start + 1; +define exported symbol __CONTAINER_IMG_OFFSET = start(TEXT_region) - start(CONTAINER_region); +define exported symbol __CONTAINER_IMG_LOAD_ADDR = start(TEXT_region); +define exported symbol __CONTAINER_IMG_ENTRY_ADDR = start(TEXT_region); +if (isdefinedsymbol(__use_shmem__)) { + define exported symbol rpmsg_sh_mem_start = m_rpmsg_sh_mem_start; + define exported symbol rpmsg_sh_mem_end = m_rpmsg_sh_mem_end; + define exported symbol __RPMSG_SH_MEM_START = m_rpmsg_sh_mem_start; + define exported symbol __RPMSG_SH_MEM_SIZE = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1; +} + +/* Block definition */ +define block RW { readwrite }; +define block ZI { zi }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; +define block QACCESS_CODE { section CodeQuickAccess }; +define block QACCESS_DATA { section DataQuickAccess }; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block CORE1_IMAGE_BLOCK with alignment = 16, maximum size = m_core1_image_maximum_size { section __core1_image }; + +define block RO with fixed order { readonly section .intvec, readonly, block CORE1_IMAGE_BLOCK }; + +initialize by copy { readwrite, section .textrw, section DataQuickAccess, section CodeQuickAccess, ro code object fsl_flexspi.o, ro code object drv_flexspi_nor_flash.o, ro code object drv_flexspi.o }; +do not initialize { section .noinit }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +keep{ section .boot_hdr.conf, section .boot_hdr.xmcd_data, section .boot_hdr.container }; + +place in FCB_region { section .boot_hdr.conf }; +place in XMCD_region { section .boot_hdr.xmcd_data }; +place in CONTAINER_region { section .boot_hdr.container }; +place in TEXT_region { first block RO }; +place in QACODE_region { section .textrw, block QACCESS_CODE }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { block QACCESS_DATA }; +place in NCACHE_region { block NCACHE_VAR }; +place in CSTACK_region { block CSTACK }; +if (isdefinedsymbol(__heap_noncacheable__)) { + place in NCACHE_region { last block HEAP }; +} else { + place in HEAP_region { last block HEAP }; +} +if (isdefinedsymbol(__use_shmem__)) { + place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor.ld b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor.ld index 2e4cafeabe52..5f45351e231c 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor.ld +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor.ld @@ -168,8 +168,8 @@ SECTIONS .text : { . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ + *(EXCLUDE_FILE(*fsl_flexspi.o *drv_flexspi_nor_flash.o *drv_flexspi.o) .text) + *(EXCLUDE_FILE(*fsl_flexspi.o *drv_flexspi_nor_flash.o *drv_flexspi.o) .text*) *(.rodata) /* .rodata sections (constants, strings, etc.) */ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ *(.glue_7) /* glue arm to thumb code */ @@ -296,6 +296,11 @@ SECTIONS . = ALIGN(32); __ram_function_start__ = .; *(CodeQuickAccess) + /* The FlexSPI drivers must run from TCM while the flash is being + reconfigured, mirroring the Keil/IAR QuickAccess placement. */ + *fsl_flexspi.o(.text*) + *drv_flexspi_nor_flash.o(.text*) + *drv_flexspi.o(.text*) . = ALIGN(128); __ram_function_end__ = .; } > m_qacode diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor_hyperram.icf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor_hyperram.icf index 263c64ce5dcc..e96eebb4b533 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor_hyperram.icf +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor_hyperram.icf @@ -1,187 +1,187 @@ -/* -** ################################################################### -** Processors: MIMXRT1189CVM8B_cm33 -** MIMXRT1189CVM8C_cm33 -** MIMXRT1189XVM8B_cm33 -** MIMXRT1189XVM8C_cm33 -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: IMXRT1180RM, Rev 5, 01/2024 -** Version: rev. 2.0, 2024-01-18 -** Build: b250310 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2025 NXP -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -/* Board memory map */ - -define symbol m_code_tcm_start = 0x0FFE0000; -define symbol m_code_tcm_size = 0x00020000; - -define symbol m_system_tcm_start = 0x20000000; -define symbol m_system_tcm_size = 0x00020000; - -define symbol m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */ -define symbol m_ocram1_size = 0x0007C000; - -define symbol m_ocram2_start = 0x20500000; -define symbol m_ocram2_size = 0x00040000; - -/* CM33 use last 2M bytes space of sdram and hyperram for dual image framework */ -define symbol m_sdram_start = isdefinedsymbol(__dual_image__) ? 0x81E00000 : 0x80000000; -define symbol m_sdram_size = isdefinedsymbol(__dual_image__) ? 0x00200000 : 0x02000000; -define symbol m_hyperram_start = isdefinedsymbol(__dual_image__) ? 0x04600000 : 0x04000000; -define symbol m_hyperram_size = isdefinedsymbol(__dual_image__) ? 0x00200000 : 0x00800000; -define symbol m_flash_start = 0x28000000; -define symbol m_flash_size = 0x00800000; - -define symbol m_core1_image_maximum_size = 0x00040000; - -/* General definition */ -define symbol m_fcb_offset = 0x400; -define symbol m_fcb_size = 0x200; -define symbol m_fcb_start = m_flash_start + m_fcb_offset; -define symbol m_fcb_end = m_fcb_start + m_fcb_size - 1; - -define symbol m_xmcd_offset = 0x800; -define symbol m_xmcd_size = 0x400; -define symbol m_xmcd_start = m_flash_start + m_xmcd_offset; -define symbol m_xmcd_end = m_xmcd_start + m_xmcd_size - 1; - -define symbol m_container_offset = 0x1000; -define symbol m_container_size = 0x2000; -define symbol m_container_start = m_flash_start + m_container_offset; -define symbol m_container_end = m_container_start + m_container_size - 1; - -define symbol app_image_offset = 0x0000B000; -define symbol vector_table_size = 0x00000400; -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x01000; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x08000; -} - -define symbol m_qacode_start = m_code_tcm_start + (isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0); -define symbol m_qacode_end = m_code_tcm_start + m_code_tcm_size - 1; -define symbol m_qadata_start = m_system_tcm_start; -define symbol m_qadata_end = m_system_tcm_start + m_system_tcm_size - 1; -define symbol m_ram_vector_table_start = m_code_tcm_start; - -/* Target specific definition, code & data allocation */ -define symbol m_code_size = m_flash_size - app_image_offset; -define symbol m_data_size = m_hyperram_size; -define symbol m_ncache_size = isdefinedsymbol(__multicore__) ? 0x20000 : 0x40000; /* m_ncache_size must be 2^N */ -define symbol m_shmem_size = m_ocram2_size; /* m_shmem_size must be 2^N */ - -define symbol m_ocram1_size_for_cm7 = isdefinedsymbol(__multicore__) ? 0x40000 : 0; - -define symbol m_ram_vector_table_size = isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0; - -define symbol m_text_start = m_flash_start + app_image_offset; -define symbol m_text_end = m_text_start + m_code_size - 1; -define symbol m_interrupts_start = m_text_start; - -define symbol m_data_start = m_hyperram_start; -define symbol m_data_end = m_data_start + m_data_size - 1; - -define symbol m_ncache_start = m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7 - m_ncache_size; -define symbol m_ncache_end = m_ncache_start + m_ncache_size - 1; - -define symbol m_heap_start = m_ocram1_start; -define symbol m_heap_end = m_ncache_start - 1; - -if (isdefinedsymbol(__use_shmem__)) { - define symbol m_rpmsg_sh_mem_start = m_ocram2_start; - define symbol m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; -} - -/* Region definition */ -define memory mem with size = 4G; -define region FCB_region = mem:[from m_fcb_start to m_fcb_end]; -define region XMCD_region = mem:[from m_xmcd_start to m_xmcd_end]; -define region CONTAINER_region = mem:[from m_container_start to m_container_end]; -define region TEXT_region = mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; -define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; -define region HEAP_region = mem:[from m_heap_start to m_heap_end]; -define region QACODE_region = mem:[from m_qacode_start to m_qacode_end]; -define region QADATA_region = mem:[from m_qadata_start to m_qadata_end]; -if (isdefinedsymbol(__use_shmem__)) { - define region rpmsg_sh_mem_region = mem:[from m_rpmsg_sh_mem_start to m_rpmsg_sh_mem_end]; -} - -/* Exported symbol definition */ -define exported symbol __VECTOR_TABLE = m_interrupts_start; -define exported symbol __VECTOR_RAM = m_ram_vector_table_start; -define exported symbol __RAM_VECTOR_TABLE_SIZE = m_ram_vector_table_size; -define exported symbol __NCACHE_REGION_START = m_ncache_start; -define exported symbol __NCACHE_REGION_SIZE = m_ncache_end - m_ncache_start + 1; -define exported symbol __CONTAINER_IMG_OFFSET = start(TEXT_region) - start(CONTAINER_region); -define exported symbol __CONTAINER_IMG_LOAD_ADDR = start(TEXT_region); -define exported symbol __CONTAINER_IMG_ENTRY_ADDR = start(TEXT_region); -if (isdefinedsymbol(__use_shmem__)) { - define exported symbol rpmsg_sh_mem_start = m_rpmsg_sh_mem_start; - define exported symbol rpmsg_sh_mem_end = m_rpmsg_sh_mem_end; - define exported symbol __RPMSG_SH_MEM_START = m_rpmsg_sh_mem_start; - define exported symbol __RPMSG_SH_MEM_SIZE = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1; -} - -/* Block definition */ -define block RW { readwrite }; -define block ZI { zi }; -define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; -define block QACCESS_CODE { section CodeQuickAccess }; -define block QACCESS_DATA { section DataQuickAccess }; -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block CORE1_IMAGE_BLOCK with alignment = 16, maximum size = m_core1_image_maximum_size { section __core1_image }; - -/* cache line size = 16 bytes */ -define block CACHE_LINE_DATA_ZI with alignment = 16, end alignment = 16 { section CacheLineData }; -define block CACHE_LINE_DATA_RW with alignment = 16, end alignment = 16 { section CacheLineData.init }; - -define block RO with fixed order { readonly section .intvec, readonly, block CORE1_IMAGE_BLOCK }; - -initialize by copy { readwrite, section .textrw, section DataQuickAccess, section CodeQuickAccess, ro code object fsl_flexspi.o, ro code object drv_flexspi_nor_flash.o, ro code object drv_flexspi.o }; -do not initialize { section .noinit }; -if (isdefinedsymbol(__use_shmem__)) { - do not initialize { section rpmsg_sh_mem_section }; -} - -keep{ section .boot_hdr.conf, section .boot_hdr.xmcd_data, section .boot_hdr.container }; - -place in FCB_region { section .boot_hdr.conf }; -place in XMCD_region { section .boot_hdr.xmcd_data }; -place in CONTAINER_region { section .boot_hdr.container }; -place in TEXT_region { first block RO }; -place in QACODE_region { section .textrw, block QACCESS_CODE }; -place in DATA_region { block RW, block CACHE_LINE_DATA_RW }; -place in DATA_region { block ZI, block CACHE_LINE_DATA_ZI }; -place in QADATA_region { block QACCESS_DATA }; -place in NCACHE_region { block NCACHE_VAR }; -place in CSTACK_region { block CSTACK }; -if (isdefinedsymbol(__heap_noncacheable__)) { - place in NCACHE_region { last block HEAP }; -} else { - place in HEAP_region { last block HEAP }; -} -if (isdefinedsymbol(__use_shmem__)) { - place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; -} +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm33 +** MIMXRT1189CVM8C_cm33 +** MIMXRT1189XVM8B_cm33 +** MIMXRT1189XVM8C_cm33 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Board memory map */ + +define symbol m_code_tcm_start = 0x0FFE0000; +define symbol m_code_tcm_size = 0x00020000; + +define symbol m_system_tcm_start = 0x20000000; +define symbol m_system_tcm_size = 0x00020000; + +define symbol m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */ +define symbol m_ocram1_size = 0x0007C000; + +define symbol m_ocram2_start = 0x20500000; +define symbol m_ocram2_size = 0x00040000; + +/* CM33 use last 2M bytes space of sdram and hyperram for dual image framework */ +define symbol m_sdram_start = isdefinedsymbol(__dual_image__) ? 0x81E00000 : 0x80000000; +define symbol m_sdram_size = isdefinedsymbol(__dual_image__) ? 0x00200000 : 0x02000000; +define symbol m_hyperram_start = isdefinedsymbol(__dual_image__) ? 0x04600000 : 0x04000000; +define symbol m_hyperram_size = isdefinedsymbol(__dual_image__) ? 0x00200000 : 0x00800000; +define symbol m_flash_start = 0x28000000; +define symbol m_flash_size = 0x00800000; + +define symbol m_core1_image_maximum_size = 0x00040000; + +/* General definition */ +define symbol m_fcb_offset = 0x400; +define symbol m_fcb_size = 0x200; +define symbol m_fcb_start = m_flash_start + m_fcb_offset; +define symbol m_fcb_end = m_fcb_start + m_fcb_size - 1; + +define symbol m_xmcd_offset = 0x800; +define symbol m_xmcd_size = 0x400; +define symbol m_xmcd_start = m_flash_start + m_xmcd_offset; +define symbol m_xmcd_end = m_xmcd_start + m_xmcd_size - 1; + +define symbol m_container_offset = 0x1000; +define symbol m_container_size = 0x2000; +define symbol m_container_start = m_flash_start + m_container_offset; +define symbol m_container_end = m_container_start + m_container_size - 1; + +define symbol app_image_offset = 0x0000B000; +define symbol vector_table_size = 0x00000400; +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x01000; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x08000; +} + +define symbol m_qacode_start = m_code_tcm_start + (isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0); +define symbol m_qacode_end = m_code_tcm_start + m_code_tcm_size - 1; +define symbol m_qadata_start = m_system_tcm_start; +define symbol m_qadata_end = m_system_tcm_start + m_system_tcm_size - 1; +define symbol m_ram_vector_table_start = m_code_tcm_start; + +/* Target specific definition, code & data allocation */ +define symbol m_code_size = m_flash_size - app_image_offset; +define symbol m_data_size = m_hyperram_size; +define symbol m_ncache_size = isdefinedsymbol(__multicore__) ? 0x20000 : 0x40000; /* m_ncache_size must be 2^N */ +define symbol m_shmem_size = m_ocram2_size; /* m_shmem_size must be 2^N */ + +define symbol m_ocram1_size_for_cm7 = isdefinedsymbol(__multicore__) ? 0x40000 : 0; + +define symbol m_ram_vector_table_size = isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0; + +define symbol m_text_start = m_flash_start + app_image_offset; +define symbol m_text_end = m_text_start + m_code_size - 1; +define symbol m_interrupts_start = m_text_start; + +define symbol m_data_start = m_hyperram_start; +define symbol m_data_end = m_data_start + m_data_size - 1; + +define symbol m_ncache_start = m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7 - m_ncache_size; +define symbol m_ncache_end = m_ncache_start + m_ncache_size - 1; + +define symbol m_heap_start = m_ocram1_start; +define symbol m_heap_end = m_ncache_start - 1; + +if (isdefinedsymbol(__use_shmem__)) { + define symbol m_rpmsg_sh_mem_start = m_ocram2_start; + define symbol m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; +} + +/* Region definition */ +define memory mem with size = 4G; +define region FCB_region = mem:[from m_fcb_start to m_fcb_end]; +define region XMCD_region = mem:[from m_xmcd_start to m_xmcd_end]; +define region CONTAINER_region = mem:[from m_container_start to m_container_end]; +define region TEXT_region = mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; +define region HEAP_region = mem:[from m_heap_start to m_heap_end]; +define region QACODE_region = mem:[from m_qacode_start to m_qacode_end]; +define region QADATA_region = mem:[from m_qadata_start to m_qadata_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from m_rpmsg_sh_mem_start to m_rpmsg_sh_mem_end]; +} + +/* Exported symbol definition */ +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_ram_vector_table_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = m_ram_vector_table_size; +define exported symbol __NCACHE_REGION_START = m_ncache_start; +define exported symbol __NCACHE_REGION_SIZE = m_ncache_end - m_ncache_start + 1; +define exported symbol __CONTAINER_IMG_OFFSET = start(TEXT_region) - start(CONTAINER_region); +define exported symbol __CONTAINER_IMG_LOAD_ADDR = start(TEXT_region); +define exported symbol __CONTAINER_IMG_ENTRY_ADDR = start(TEXT_region); +if (isdefinedsymbol(__use_shmem__)) { + define exported symbol rpmsg_sh_mem_start = m_rpmsg_sh_mem_start; + define exported symbol rpmsg_sh_mem_end = m_rpmsg_sh_mem_end; + define exported symbol __RPMSG_SH_MEM_START = m_rpmsg_sh_mem_start; + define exported symbol __RPMSG_SH_MEM_SIZE = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1; +} + +/* Block definition */ +define block RW { readwrite }; +define block ZI { zi }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; +define block QACCESS_CODE { section CodeQuickAccess }; +define block QACCESS_DATA { section DataQuickAccess }; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block CORE1_IMAGE_BLOCK with alignment = 16, maximum size = m_core1_image_maximum_size { section __core1_image }; + +/* cache line size = 16 bytes */ +define block CACHE_LINE_DATA_ZI with alignment = 16, end alignment = 16 { section CacheLineData }; +define block CACHE_LINE_DATA_RW with alignment = 16, end alignment = 16 { section CacheLineData.init }; + +define block RO with fixed order { readonly section .intvec, readonly, block CORE1_IMAGE_BLOCK }; + +initialize by copy { readwrite, section .textrw, section DataQuickAccess, section CodeQuickAccess, ro code object fsl_flexspi.o, ro code object drv_flexspi_nor_flash.o, ro code object drv_flexspi.o }; +do not initialize { section .noinit }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +keep{ section .boot_hdr.conf, section .boot_hdr.xmcd_data, section .boot_hdr.container }; + +place in FCB_region { section .boot_hdr.conf }; +place in XMCD_region { section .boot_hdr.xmcd_data }; +place in CONTAINER_region { section .boot_hdr.container }; +place in TEXT_region { first block RO }; +place in QACODE_region { section .textrw, block QACCESS_CODE }; +place in DATA_region { block RW, block CACHE_LINE_DATA_RW }; +place in DATA_region { block ZI, block CACHE_LINE_DATA_ZI }; +place in QADATA_region { block QACCESS_DATA }; +place in NCACHE_region { block NCACHE_VAR }; +place in CSTACK_region { block CSTACK }; +if (isdefinedsymbol(__heap_noncacheable__)) { + place in NCACHE_region { last block HEAP }; +} else { + place in HEAP_region { last block HEAP }; +} +if (isdefinedsymbol(__use_shmem__)) { + place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor_hyperram.ld b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor_hyperram.ld index 7dd7070dd5a4..62106ca6dbb8 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor_hyperram.ld +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_flexspi_nor_hyperram.ld @@ -168,8 +168,8 @@ SECTIONS .text : { . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ + *(EXCLUDE_FILE(*fsl_flexspi.o *drv_flexspi_nor_flash.o *drv_flexspi.o) .text) + *(EXCLUDE_FILE(*fsl_flexspi.o *drv_flexspi_nor_flash.o *drv_flexspi.o) .text*) *(.rodata) /* .rodata sections (constants, strings, etc.) */ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ *(.glue_7) /* glue arm to thumb code */ @@ -297,6 +297,11 @@ SECTIONS . = ALIGN(32); __ram_function_start__ = .; *(CodeQuickAccess) + /* The FlexSPI drivers must run from TCM while the flash is being + reconfigured, mirroring the Keil/IAR QuickAccess placement. */ + *fsl_flexspi.o(.text*) + *drv_flexspi_nor_flash.o(.text*) + *drv_flexspi.o(.text*) . = ALIGN(128); __ram_function_end__ = .; } > m_qacode diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_ram_industry.icf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_ram_industry.icf new file mode 100644 index 000000000000..5f3796333fce --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_ram_industry.icf @@ -0,0 +1,176 @@ +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm33 +** MIMXRT1189CVM8C_cm33 +** MIMXRT1189XVM8B_cm33 +** MIMXRT1189XVM8C_cm33 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** Industrial Ethernet configuration: +** - CM33 uses 256KB TCM only (128KB code TCM + 128KB system TCM), +** OCRAM1 is reserved for CM7. +** - CM33 uses 128KB OCRAM2 exclusively (64KB heap + 64KB non-cacheable data). +** - 32KB OCRAM2 is reserved as RPMsg shared memory. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Board memory map */ + +define symbol m_code_tcm_start = 0x0FFE0000; +define symbol m_code_tcm_size = 0x00020000; + +define symbol m_system_tcm_start = 0x20000000; +define symbol m_system_tcm_size = 0x00020000; + +/* OCRAM1 is not used by CM33 in this configuration, it is reserved for CM7 */ +define symbol m_ocram2_start = 0x20500000; +define symbol m_ocram2_size = 0x00040000; + +/* CM33 use last 2M bytes space of sdram and hyperram for dual image framework */ +define symbol m_sdram_start = isdefinedsymbol(__dual_image__) ? 0x81E00000 : 0x80000000; +define symbol m_sdram_size = isdefinedsymbol(__dual_image__) ? 0x00200000 : 0x02000000; +define symbol m_hyperram_start = isdefinedsymbol(__dual_image__) ? 0x04600000 : 0x04000000; +define symbol m_hyperram_size = isdefinedsymbol(__dual_image__) ? 0x00200000 : 0x00800000; +define symbol m_flash_start = 0x28000000; +define symbol m_flash_size = 0x01000000; + +define symbol m_core1_image_maximum_size = 0x00040000; + +/* General definition */ +define symbol app_image_offset = isdefinedsymbol(__dual_image__) ? 0x0010B000 : 0x0000B000; +define symbol vector_table_size = 0x00000400; +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x01000; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x10000; +} + +define symbol m_qacode_start = m_code_tcm_start + (isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0); +define symbol m_qacode_end = m_code_tcm_start + m_code_tcm_size - 1; +define symbol m_qadata_start = m_system_tcm_start; +define symbol m_qadata_end = m_system_tcm_start + m_system_tcm_size - 1; +define symbol m_ram_vector_table_start = m_code_tcm_start; + +/* Target specific definition, code & data allocation */ +define symbol m_code_size = m_code_tcm_size; +define symbol m_data_size = m_system_tcm_size; + +/* Industrial Ethernet configuration: + * CM33 only uses 256KB TCM and 128KB OCRAM2, plus 32KB OCRAM2 as shared memory. + * OCRAM2 layout (256KB @ 0x20500000): + * [0x20500000, 0x2050FFFF] 64KB CM33 heap + * [0x20510000, 0x2051FFFF] 64KB non-cacheable data (NCACHE) + * [0x20520000, 0x20537FFF] 96KB reserved for CM7 + * [0x20538000, 0x2053FFFF] 32KB RPMsg shared memory + * NCACHE and shared memory sizes must be 2^N and the start addresses must be + * multiples of the size so that the MPU configuration in BOARD_ConfigMPU() + * stays valid. + */ +define symbol m_heap_start = m_ocram2_start; /* 0x20500000 */ + +if (isdefinedsymbol(__heap_noncacheable__)) { + /* heap is placed at the end of the non-cacheable region */ + define symbol m_ncache_size = 0x20000; /* 128KB, must be 2^N */ + define symbol m_ncache_start = m_heap_start; +} else { + define symbol m_ncache_size = 0x10000; /* 64KB, must be 2^N */ + define symbol m_ncache_start = m_heap_start + m_ncache_size; /* 0x20510000 */ +} +define symbol m_ncache_end = m_ncache_start + m_ncache_size - 1; +define symbol m_heap_end = m_ncache_start - 1; + +define symbol m_shmem_size = 0x8000; /* 32KB shared memory, must be 2^N */ +if (isdefinedsymbol(__use_shmem__)) { + define symbol m_rpmsg_sh_mem_start = m_ocram2_start + m_ocram2_size - m_shmem_size; /* 0x20538000 */ + define symbol m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; +} + +define symbol m_ram_vector_table_size = isdefinedsymbol(__ram_vector_table__) ? 0 : 0; + +define symbol m_text_start = m_code_tcm_start; +define symbol m_text_end = m_text_start + m_code_size - 1; +define symbol m_interrupts_start = m_text_start; + +define symbol m_data_start = m_system_tcm_start; +define symbol m_data_end = m_data_start + m_data_size - 1; + +/* Exported symbol definition */ +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_ram_vector_table_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = m_ram_vector_table_size; +define exported symbol __NCACHE_REGION_START = m_ncache_start; +define exported symbol __NCACHE_REGION_SIZE = m_ncache_end - m_ncache_start + 1; +if (isdefinedsymbol(__use_shmem__)) { + define exported symbol rpmsg_sh_mem_start = m_rpmsg_sh_mem_start; + define exported symbol rpmsg_sh_mem_end = m_rpmsg_sh_mem_end; + define exported symbol __RPMSG_SH_MEM_START = m_rpmsg_sh_mem_start; + define exported symbol __RPMSG_SH_MEM_SIZE = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1; +} + +/* Region definition */ +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; +define region HEAP_region = mem:[from m_heap_start to m_heap_end]; +define region QACODE_region = mem:[from m_qacode_start to m_qacode_end]; +define region QADATA_region = mem:[from m_qadata_start to m_qadata_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from m_rpmsg_sh_mem_start to m_rpmsg_sh_mem_end]; +} + +/* Block definition */ +define block RW { readwrite }; +define block ZI { zi }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; +define block QACCESS_CODE { section CodeQuickAccess }; +define block QACCESS_DATA { section DataQuickAccess }; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block CORE1_IMAGE_BLOCK with alignment = 16, maximum size = m_core1_image_maximum_size { section __core1_image }; + +initialize by copy { readwrite, section .textrw, section DataQuickAccess }; +do not initialize { section .noinit }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place in TEXT_region { readonly }; +place in TEXT_region { block CORE1_IMAGE_BLOCK }; +place in TEXT_region { block QACCESS_CODE }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { block QACCESS_DATA }; +place in NCACHE_region { block NCACHE_VAR }; +place in CSTACK_region { block CSTACK }; +if (isdefinedsymbol(__heap_noncacheable__)) { + place in NCACHE_region { last block HEAP }; +} else { + place in HEAP_region { last block HEAP }; +} +if (isdefinedsymbol(__use_shmem__)) { + place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_ram_industry.ld b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_ram_industry.ld new file mode 100644 index 000000000000..68657644f29f --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_ram_industry.ld @@ -0,0 +1,356 @@ +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm33 +** MIMXRT1189CVM8C_cm33 +** MIMXRT1189XVM8B_cm33 +** MIMXRT1189XVM8C_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the GNU C Compiler +** Industrial Ethernet configuration: +** - CM33 uses 256KB TCM only (128KB code TCM + 128KB system TCM), +** OCRAM1 is reserved for CM7. +** - CM33 uses 128KB OCRAM2 exclusively (64KB heap + 64KB non-cacheable data). +** - 32KB OCRAM2 is reserved as RPMsg shared memory. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Board memory map */ +m_code_tcm_start = 0x0FFE0000; +m_code_tcm_size = 0x00020000; +m_system_tcm_start = 0x20000000; +m_system_tcm_size = 0x00020000; + +/* OCRAM1 is not used by CM33 in this configuration, it is reserved for CM7 */ +m_ocram2_start = 0x20500000; +m_ocram2_size = 0x00040000; + +/* CM33 use last 2M bytes space of sdram and hyperram for dual image framework */ +m_sdram_start = DEFINED(__dual_image__) ? 0x81E00000 : 0x80000000; +m_sdram_size = DEFINED(__dual_image__) ? 0x00200000 : 0x02000000; +m_hyperram_start = DEFINED(__dual_image__) ? 0x04600000 : 0x04000000; +m_hyperram_size = DEFINED(__dual_image__) ? 0x00200000 : 0x00800000; +m_flash_start = 0x28000000; +m_flash_size = 0x01000000; + +m_core1_image_maximum_size = 0x00040000; + +/* General definition */ +app_image_offset = DEFINED(__dual_image__) ? 0x0010B000 : 0x0000B000; +vector_table_size = 0x00000400; +m_qacode_start = m_code_tcm_start + (DEFINED(__ram_vector_table__) ? vector_table_size : 0); +m_qacode_end = m_code_tcm_start + m_code_tcm_size - 1; +m_qadata_start = m_system_tcm_start; +m_qadata_end = m_system_tcm_start + m_system_tcm_size - 1; +m_ram_vector_table_start = m_code_tcm_start; +m_stack_size = DEFINED(__stack_size__) ? __stack_size__ : 0x1000; +m_heap_size = DEFINED(__heap_size__) ? __heap_size__ : 0x10000; + +/* Target specific definition, code & data allocation */ +m_code_size = m_code_tcm_size - vector_table_size; +m_data_size = m_system_tcm_size; + +/* Industrial Ethernet configuration: + * CM33 only uses 256KB TCM and 128KB OCRAM2, plus 32KB OCRAM2 as shared memory. + * OCRAM2 layout (256KB @ 0x20500000): + * [0x20500000, 0x2050FFFF] 64KB CM33 heap + * [0x20510000, 0x2051FFFF] 64KB non-cacheable data (NCACHE) + * [0x20520000, 0x20537FFF] 96KB reserved for CM7 + * [0x20538000, 0x2053FFFF] 32KB RPMsg shared memory + * NCACHE and shared memory sizes must be 2^N and the start addresses must be + * multiples of the size so that the MPU configuration in BOARD_ConfigMPU() + * stays valid. + */ +m_ncache_size = DEFINED(__heap_noncacheable__) ? 0x20000 : 0x10000; /* must be 2^N */ +m_ncache_start = DEFINED(__heap_noncacheable__) ? m_ocram2_start : m_ocram2_start + m_ncache_size; /* 0x20510000 */ +m_shmem_size = 0x8000; /* 32KB shared memory, must be 2^N */ + +m_ram_vector_table_size = DEFINED(__ram_vector_table__) ? 0 : 0; + +m_interrupts_start = m_code_tcm_start; +m_interrupts_end = m_interrupts_start + vector_table_size - 1; + +m_text_start = m_interrupts_end + 1; +m_text_end = m_text_start + m_code_size - 1; + +m_data_start = m_system_tcm_start; +m_data_end = m_data_start + m_data_size - 1; + +m_ncache_end = m_ncache_start + m_ncache_size - 1 - (DEFINED(__heap_noncacheable__) ? m_heap_size : 0); + +m_heap_start = DEFINED(__heap_noncacheable__) ? m_ncache_end + 1 : m_ocram2_start; /* 0x20500000 */ +m_heap_end = m_heap_start + m_heap_size - 1; + +m_rpmsg_sh_mem_start = m_ocram2_start + m_ocram2_size - m_shmem_size; /* 0x20538000 */ +m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; + +/* Exported symbol definition */ +__VECTOR_TABLE = m_interrupts_start; +__VECTOR_RAM = m_ram_vector_table_start; +__RAM_VECTOR_TABLE_SIZE_BYTES = m_ram_vector_table_size; + +__NCACHE_REGION_START = m_ncache_start; +__NCACHE_REGION_SIZE = m_ncache_size; +__RPMSG_SH_MEM_START = DEFINED(__use_shmem__)? m_rpmsg_sh_mem_start : 0; +__RPMSG_SH_MEM_SIZE = DEFINED(__use_shmem__)? m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1 : 0; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts_ram (RX) : ORIGIN = m_ram_vector_table_start, LENGTH = __RAM_VECTOR_TABLE_SIZE_BYTES + m_interrupts (RX) : ORIGIN = m_interrupts_start, LENGTH = m_interrupts_end - m_interrupts_start + 1 + m_text (RX) : ORIGIN = m_text_start, LENGTH = m_text_end - m_text_start + 1 + m_data (RW) : ORIGIN = m_data_start, LENGTH = m_data_end - m_data_start + 1 + m_ncache (RW) : ORIGIN = m_ncache_start, LENGTH = m_ncache_end - m_ncache_start + 1 + m_heap (RW) : ORIGIN = m_heap_start, LENGTH = m_heap_end - m_heap_start + 1 + m_qacode (RX) : ORIGIN = m_qacode_start, LENGTH = m_qacode_end - m_qacode_start + 1 + m_qadata (RW) : ORIGIN = m_qadata_start, LENGTH = m_qadata_end - m_qadata_start + 1 + m_rpmsg (RW) : ORIGIN = m_rpmsg_sh_mem_start, LENGTH = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first */ + .interrupts : + { + . = ALIGN(4); + __Vectors = .; + KEEP(*(.isr_vector)) /* Vector table and startup code */ + . = ALIGN(4); + } > m_interrupts + + .interrupts_ram : + { + . = ALIGN(4); + . += __RAM_VECTOR_TABLE_SIZE_BYTES; + . = ALIGN(4); + } > m_interrupts_ram + + /* The program code */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + *(CodeQuickAccess) + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(16); + core1_image_start = .; + KEEP (*(.core1_code)) + *(.core1_code*) + core1_image_end = .; + . = ALIGN(4) ; + } > m_text + + ASSERT((core1_image_end - core1_image_start) <= m_core1_image_maximum_size, "Core1 image size exceeds the limit") + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + + __data_flash_start = .; /* Symbol is used by startup for data initialization */ + .data : AT(__data_flash_start) + { + . = ALIGN(4); + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(DataQuickAccess) /* quick access data section */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __ram_function_flash_start = __data_flash_start + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM code initialization */ + .ram_function : AT(__ram_function_flash_start) + { + . = ALIGN(32); + __ram_function_start__ = .; + . = ALIGN(128); + __ram_function_end__ = .; + } > m_qacode + + __noncache_data_flash_start = __ram_function_flash_start + (__ram_function_end__ - __ram_function_start__); + .ncache.init : AT(__noncache_data_flash_start) + { + . = ALIGN(4); + __noncache_data_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncache_data_end__ = .; /* create a global symbol at ncache data end */ + } > m_ncache + + .ncache : + { + . = ALIGN(4); + __noncache_bss_start__ = .; /* define a global symbol at ncache bss start */ + *(NonCacheable) + . = ALIGN(4); + __noncache_bss_end__ = .; /* define a global symbol at ncache bss end */ + } > m_ncache + + __qadata_flash_start = __noncache_data_flash_start + (__noncache_data_end__ - __noncache_data_start__); + .qadata : AT(__qadata_flash_start) + { + . = ALIGN(4); + __qadata_start__ = .; + . = ALIGN(4); + __qadata_end__ = .; + } > m_qadata + + text_data_end = __qadata_flash_start + (__qadata_end__ - __qadata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(text_data_end < text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > m_data + + .rpmsg : + { + *(.noinit.$rpmsg_sh_mem) + } > m_rpmsg + + .heap : + { + . = ALIGN(8); + __HeapBase = .; + end = .; + . += m_heap_size; + __HeapLimit = .; /* Add for _sbrk */ + } > m_heap + + .stack : + { + . = ALIGN(8); + __StackStart = .; + . += m_stack_size; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - m_stack_size; + PROVIDE(__stack = __StackTop); + PROVIDE (__stack_size = m_stack_size); + ASSERT(__StackLimit >= __StackStart, "region m_data overflowed with stack and heap") + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_ram_industry.scf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_ram_industry.scf new file mode 100644 index 000000000000..1064feb4ecc3 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/MIMXRT1189xxxxx_cm33_ram_industry.scf @@ -0,0 +1,212 @@ +#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m33 -E -x c +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm33 +** MIMXRT1189CVM8C_cm33 +** MIMXRT1189XVM8B_cm33 +** MIMXRT1189XVM8C_cm33 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** Industrial Ethernet configuration: +** - CM33 uses 256KB TCM only (128KB code TCM + 128KB system TCM), +** OCRAM1 is reserved for CM7. +** - CM33 uses 128KB OCRAM2 exclusively (64KB heap + 64KB non-cacheable data). +** - 32KB OCRAM2 is reserved as RPMsg shared memory. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* Board memory map */ + +#define m_code_tcm_start 0x0FFE0000 +#define m_code_tcm_size 0x00020000 + +#define m_system_tcm_start 0x20000000 +#define m_system_tcm_size 0x00020000 + +/* OCRAM1 is not used by CM33 in this configuration, it is reserved for CM7 */ +#define m_ocram2_start 0x20500000 +#define m_ocram2_size 0x00040000 + +#if defined(__dual_image__) +/* CM33 use last 2M bytes space of sdram and hyperram for dual image framework */ +#define m_sdram_start 0x81E00000 +#define m_sdram_size 0x00200000 +#define m_hyperram_start 0x04600000 +#define m_hyperram_size 0x00200000 +#else +#define m_sdram_start 0x80000000 +#define m_sdram_size 0x02000000 +#define m_hyperram_start 0x04000000 +#define m_hyperram_size 0x00800000 +#endif + +#define m_flash_start 0x28000000 +#define m_flash_size 0x01000000 +#define m_core1_image_maximum_size 0x00040000 + +/* General definition */ +#if defined(__dual_image__) +#define app_image_offset 0x0010B000 +#else +#define app_image_offset 0x0000B000 +#endif + +#define vector_table_size 0x400 +#define m_ram_vector_table_start m_code_tcm_start + +#if defined(__stack_size__) + #define stack_size __stack_size__ +#else + #define stack_size 0x01000 +#endif + +#if defined(__heap_size__) + #define heap_size __heap_size__ +#else + #define heap_size 0x10000 +#endif + +/* Target specific definition, code & data allocation */ +#if defined(__ram_vector_table__) +#define m_ram_vector_table_size 0 +#else +#define m_ram_vector_table_size 0 +#endif + +#define m_qacode_start m_code_tcm_start + m_ram_vector_table_size +#define m_qadata_start m_system_tcm_start +#define m_qacode_size 0 +#define m_qadata_size 0 + +#define m_text_size m_code_tcm_size +#define m_data_size m_system_tcm_size + +/* Industrial Ethernet configuration: + * CM33 only uses 256KB TCM and 128KB OCRAM2, plus 32KB OCRAM2 as shared memory. + * OCRAM2 layout (256KB @ 0x20500000): + * [0x20500000, 0x2050FFFF] 64KB CM33 heap + * [0x20510000, 0x2051FFFF] 64KB non-cacheable data (NCACHE) + * [0x20520000, 0x20537FFF] 96KB reserved for CM7 + * [0x20538000, 0x2053FFFF] 32KB RPMsg shared memory + * NCACHE and shared memory sizes must be 2^N and the start addresses must be + * multiples of the size so that the MPU configuration in BOARD_ConfigMPU() + * stays valid. + */ +#define m_heap_start m_ocram2_start /* 0x20500000 */ +#define m_heap_max_size 0x10000 /* 64KB heap region */ + +#if defined(__heap_noncacheable__) +/* heap is placed at the end of the non-cacheable region */ +#define m_ncache_size 0x20000 /* 128KB, must be 2^N */ +#define m_ncache_start m_heap_start +#else +#define m_ncache_size 0x10000 /* 64KB, must be 2^N */ +#define m_ncache_start m_heap_start + m_heap_max_size /* 0x20510000 */ +#endif + +#define m_shmem_size 0x8000 /* 32KB shared memory, must be 2^N */ +#define m_shmem_start m_ocram2_start + m_ocram2_size - m_shmem_size /* 0x20538000 */ + +#define m_text_start m_code_tcm_start +#define m_interrupts_start m_text_start +#define m_data_start m_system_tcm_start + +; load region +LR_m_text m_text_start m_text_size +{ + ; load address = execution address + VECTOR_ROM m_interrupts_start FIXED vector_table_size + { + * (.isr_vector,+FIRST) + } + + VECTOR_RAM m_ram_vector_table_start EMPTY m_ram_vector_table_size + { + } + + ; load address = execution address + ER_m_text m_text_start + vector_table_size FIXED m_text_size - vector_table_size + { + * (InRoot$$Sections) + .ANY (+RO) + .ANY (CodeQuickAccess) + } + + CORE1_REGION +0 ALIGN 16 m_core1_image_maximum_size + { + .ANY (.core1_code) + } + + ER_m_QuickAccessCode m_qacode_start EMPTY m_qacode_size + { + } + + ER_m_QuickAccessData m_qadata_start EMPTY m_qadata_size + { + } + + RW_m_data m_data_start m_data_size-stack_size + { + .ANY (+RW +ZI) + .ANY (DataQuickAccess) + } + + ; ncache data + RW_m_ncache m_ncache_start m_ncache_size + { + .ANY (NonCacheable.init) + .ANY (.bss.NonCacheable) + } + +#if defined(__heap_noncacheable__) + ; Heap region growing up + ARM_LIB_HEAP +0 ALIGN 0x100 EMPTY heap_size + { + } +#endif + + ; Empty region added for MPU configuration + RW_m_ncache_aux m_ncache_start + m_ncache_size EMPTY 0 + { + } + +#if defined(__use_shmem__) + ; shared memory data + RPMSG_SH_MEM m_shmem_start m_shmem_size + { + .ANY (rpmsg_sh_mem_section) + } + + ; Empty region added for MPU configuration + RPMSG_SH_MEM_aux m_shmem_start + m_shmem_size EMPTY 0 + { + } +#endif + +#if !defined(__heap_noncacheable__) + ; Heap region growing up + ARM_LIB_HEAP m_heap_start EMPTY heap_size + { + } +#endif + + ; Stack region growing down + ARM_LIB_STACK m_data_start+m_data_size EMPTY -stack_size + { + } +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/readme.md b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/readme.md new file mode 100644 index 000000000000..466e16ed0e5b --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/readme.md @@ -0,0 +1,78 @@ +# CM33 Memory Layout + +[English version](readme_en.md) + +本目录提供四种 CM33 内存布局，每种都有 GCC `.ld`、Keil `.scf` 和 IAR `.icf` 文件。 +下表地址为 CM33 视角，结束地址包含在区域内；KB/MB 按 1024/1048576 字节计算，容量不代表实际占用。 + +## 1. 当前内存布局 + +| 内存 | 起始地址 | 结束地址 | 容量 | 用途 | +| --- | --- | --- | --- | --- | +| Code TCM | `0x0FFE0000` | `0x0FFFFFFF` | 128KB | RAM 类 target 的向量和代码；XIP 类 target 的快速代码 | +| System TCM | `0x20000000` | `0x2001FFFF` | 128KB | 普通数据和主栈，或快速数据 | +| OCRAM1 | `0x20484000` | `0x204FFFFF` | 496KB | 普通布局的 Heap 和 non-cacheable 缓冲区；工业布局留给 CM7 | +| OCRAM2 | `0x20500000` | `0x2053FFFF` | 256KB | 双核共享内存，工业布局另划分独占区域 | +| HyperRAM，非双镜像模式 | `0x04000000` | `0x047FFFFF` | 8MB | HyperRAM target 的普通数据和主栈 | +| HyperRAM，双镜像模式 | `0x04600000` | `0x047FFFFF` | 2MB | 定义 `__dual_image__` 后，CM33 使用末尾 2MB | +| FlexSPI NOR，常规 XIP 窗口 | `0x28000000` | `0x287FFFFF` | 8MB | XIP 类 target 的启动信息、向量、代码及数据初值；GCC HyperRAM 文件有例外，见下文 | + +RAM 类向量占 Code TCM 首部 1KB，代码从 `0x0FFE0400` 开始；初始化数据副本也占用 TCM 镜像空间。 +XIP 类向量位于 `0x2800B000`，普通代码从 `0x2800B400` 开始，前部空间用于启动信息。 +HyperRAM target 的快速数据仍在 System TCM，Heap 仍在 OCRAM1。当前四种布局的主要内容均不放入 SDRAM。 + +### 普通 OCRAM 布局 + +适用于 `RAM`、`FLEXSPI_NOR`、`FLEXSPI_NOR_HYPERRAM`。 +以下按双核配置（定义 `__multicore__`）且使用 cacheable Heap 说明，共享区需启用 `__use_shmem__`。 + +| 区域 | 起始地址 | 结束地址 | 容量 | +| --- | --- | --- | --- | +| CM33 Heap 可用窗口 | `0x20484000` | `0x2049FFFF` | 112KB | +| CM33 non-cacheable 缓冲区 | `0x204A0000` | `0x204BFFFF` | 128KB | +| 留给 CM7 的 OCRAM1 | `0x204C0000` | `0x204FFFFF` | 256KB | +| 双核共享 OCRAM2 | `0x20500000` | `0x2053FFFF` | 256KB | + +未定义 `__multicore__` 时，CM33 Heap 窗口扩展到 OCRAM1 低地址 240KB，non-cacheable 窗口改为高地址 256KB。 + +### 工业以太网 OCRAM 布局 + +适用于 `RAM_INDUSTRY`，以下按 cacheable Heap 说明。 + +| 区域 | 起始地址 | 结束地址 | 容量 | +| --- | --- | --- | --- | +| OCRAM1，留给 CM7 | `0x20484000` | `0x204FFFFF` | 496KB | +| CM33 Heap | `0x20500000` | `0x2050FFFF` | 64KB | +| CM33 non-cacheable 缓冲区 | `0x20510000` | `0x2051FFFF` | 64KB | +| CM7 独占额外 OCRAM2 | `0x20520000` | `0x20537FFF` | 96KB | +| 双核共享 OCRAM2 | `0x20538000` | `0x2053FFFF` | 32KB | + +CM33 使用 256KB TCM 和独占的 128KB OCRAM2，不使用 OCRAM1；双核共享区缩小到 32KB。 +CM7 应使用匹配的工业分区，不能继续把整个 OCRAM2 当作共享区。 + +## 2. 各 Target 的差异 + +| Target 类型 | 向量/普通代码 | 普通数据/主栈 | OCRAM 布局 | GCC 默认 Heap / 主栈 | Keil、IAR 默认 Heap / 主栈 | +| --- | --- | --- | --- | --- | --- | +| `RAM` | Code TCM | System TCM | 普通 | 1KB / 1KB | 32KB / 4KB | +| `RAM_INDUSTRY` | Code TCM | System TCM | 工业 | 64KB / 4KB | 64KB / 4KB | +| `FLEXSPI_NOR` | Flash XIP | System TCM | 普通 | 32KB / 4KB | 32KB / 4KB | +| `FLEXSPI_NOR_HYPERRAM` | Flash XIP | HyperRAM | 普通 | 32KB / 4KB | 32KB / 4KB | + +Heap 窗口容量不等于默认分配大小，主栈也不是各 RT-Thread 线程的独立栈。工程可覆盖堆栈大小或将 Heap 改为 non-cacheable。 +CM33 目前没有独立 `HYPERRAM` 或 `FLEXSPI_NOR_INDUSTRY` target。 + +当前 [GCC FLEXSPI_NOR_HYPERRAM 文件](MIMXRT1189xxxxx_cm33_flexspi_nor_hyperram.ld) 的 Flash 大小声明为 `0x08000000`（128MB），Keil/IAR 则为 `0x00800000`（8MB）。这只是当前文件差异，不表示板上有 128MB Flash；使用 GCC 时需核对实际容量。 + +## 3. 应用范围 + +| Target 类型 | 适用场景 | +| --- | --- | +| `RAM` | 内部 TCM 调试、小型控制和实时应用，不依赖外部 RAM | +| `RAM_INDUSTRY` | 工业以太网双核开发，CM33 承担控制或通信管理，OCRAM1 留给 CM7 | +| `FLEXSPI_NOR` | 常规 Flash XIP 应用，代码较大但普通数据可放入内部 System TCM | +| `FLEXSPI_NOR_HYPERRAM` | Flash XIP 且需要较大数据缓冲区的通信、采集或数据处理应用 | + +RAM 类镜像需要调试器或启动流程装载；HyperRAM 必须在数据和主栈使用前可访问。 +与 CM7 共用 HyperRAM 时，应选择匹配的双镜像分配；共享通信需启用共享区，工业分区需与 CM7 一致。 +链接布局只决定存放位置，不代替外设和通信初始化。 \ No newline at end of file diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/readme_en.md b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/readme_en.md new file mode 100644 index 000000000000..059fa2db2d69 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/readme_en.md @@ -0,0 +1,78 @@ +# CM33 Memory Layout + +[Chinese version](readme.md) + +This directory provides four CM33 memory layouts, each with GCC `.ld`, Keil `.scf`, and IAR `.icf` files. +Addresses are from the CM33 perspective and table end addresses are inclusive. KB/MB mean 1024/1048576 bytes; capacities are not actual usage. + +## 1. Current Memory Layout + +| Memory | Start | End | Capacity | Purpose | +| --- | --- | --- | --- | --- | +| Code TCM | `0x0FFE0000` | `0x0FFFFFFF` | 128KB | Vectors and code for RAM targets; quick-access code for XIP targets | +| System TCM | `0x20000000` | `0x2001FFFF` | 128KB | Ordinary data and main stack, or quick-access data | +| OCRAM1 | `0x20484000` | `0x204FFFFF` | 496KB | Heap and non-cacheable buffers in standard layouts; reserved for CM7 in the industry layout | +| OCRAM2 | `0x20500000` | `0x2053FFFF` | 256KB | Multicore shared memory; the industry layout also reserves exclusive areas | +| HyperRAM, without dual-image mode | `0x04000000` | `0x047FFFFF` | 8MB | Ordinary data and main stack for the HyperRAM target | +| HyperRAM, with dual-image mode | `0x04600000` | `0x047FFFFF` | 2MB | CM33 uses the final 2MB when `__dual_image__` is defined | +| FlexSPI NOR, standard XIP window | `0x28000000` | `0x287FFFFF` | 8MB | Boot information, vectors, code, and data initial values for XIP targets; the GCC HyperRAM file has an exception noted below | + +RAM targets reserve the first 1KB of Code TCM for vectors, with code starting at `0x0FFE0400`. Initialization copies also consume TCM image space. +XIP vectors are at `0x2800B000`, with ordinary code starting at `0x2800B400`; earlier Flash space is used for boot information. +The HyperRAM target keeps quick-access data in System TCM and the heap in OCRAM1. None of these four layouts places its main contents in SDRAM. + +### Standard OCRAM Layout + +Applies to `RAM`, `FLEXSPI_NOR`, and `FLEXSPI_NOR_HYPERRAM`. +The table assumes multicore configuration (`__multicore__` defined) and a cacheable heap. Shared memory requires `__use_shmem__` to be enabled. + +| Region | Start | End | Capacity | +| --- | --- | --- | --- | +| CM33 available heap window | `0x20484000` | `0x2049FFFF` | 112KB | +| CM33 non-cacheable buffers | `0x204A0000` | `0x204BFFFF` | 128KB | +| OCRAM1 reserved for CM7 | `0x204C0000` | `0x204FFFFF` | 256KB | +| Multicore shared OCRAM2 | `0x20500000` | `0x2053FFFF` | 256KB | + +Without `__multicore__`, the CM33 heap window expands to the lower 240KB of OCRAM1, and the non-cacheable window becomes the upper 256KB. + +### Industrial Ethernet OCRAM Layout + +Applies to `RAM_INDUSTRY`. The table assumes a cacheable heap. + +| Region | Start | End | Capacity | +| --- | --- | --- | --- | +| OCRAM1 reserved for CM7 | `0x20484000` | `0x204FFFFF` | 496KB | +| CM33 heap | `0x20500000` | `0x2050FFFF` | 64KB | +| CM33 non-cacheable buffers | `0x20510000` | `0x2051FFFF` | 64KB | +| CM7-exclusive additional OCRAM2 | `0x20520000` | `0x20537FFF` | 96KB | +| Multicore shared OCRAM2 | `0x20538000` | `0x2053FFFF` | 32KB | + +CM33 uses 256KB of TCM and 128KB of exclusive OCRAM2, without using OCRAM1. The shared window is reduced to 32KB. +CM7 must use a matching industry partition rather than treating all OCRAM2 as shared memory. + +## 2. Target Differences + +| Target type | Vectors/ordinary code | Ordinary data/main stack | OCRAM layout | GCC default heap / main stack | Keil, IAR default heap / main stack | +| --- | --- | --- | --- | --- | --- | +| `RAM` | Code TCM | System TCM | Standard | 1KB / 1KB | 32KB / 4KB | +| `RAM_INDUSTRY` | Code TCM | System TCM | Industry | 64KB / 4KB | 64KB / 4KB | +| `FLEXSPI_NOR` | Flash XIP | System TCM | Standard | 32KB / 4KB | 32KB / 4KB | +| `FLEXSPI_NOR_HYPERRAM` | Flash XIP | HyperRAM | Standard | 32KB / 4KB | 32KB / 4KB | + +Heap window capacity is not the default allocated heap size, and the main stack is not each RT-Thread thread's individual stack. Projects can override sizes or select a non-cacheable heap. +CM33 currently has no standalone `HYPERRAM` or `FLEXSPI_NOR_INDUSTRY` target. + +The current [GCC FLEXSPI_NOR_HYPERRAM file](MIMXRT1189xxxxx_cm33_flexspi_nor_hyperram.ld) declares a Flash size of `0x08000000` (128MB), whereas Keil/IAR declare `0x00800000` (8MB). This is a file difference, not evidence of 128MB of physical Flash. Check the actual capacity when using GCC. + +## 3. Application Scope + +| Target type | Suitable applications | +| --- | --- | +| `RAM` | Internal-TCM debugging and small control or real-time applications without external RAM | +| `RAM_INDUSTRY` | Industrial Ethernet multicore development with CM33 handling control or communication management and OCRAM1 reserved for CM7 | +| `FLEXSPI_NOR` | Conventional Flash XIP applications with larger code and ordinary data that fits in internal System TCM | +| `FLEXSPI_NOR_HYPERRAM` | Flash XIP communications, acquisition, or data-processing applications requiring larger data buffers | + +RAM images require loading by a debugger or boot flow. HyperRAM must be accessible before ordinary data and the main stack are used. +When sharing HyperRAM with CM7, use matching dual-image allocations. Shared communication requires shared memory to be enabled, and industry partitions must match CM7. +Memory layouts determine placement, not peripheral or communication initialization. \ No newline at end of file diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h index bbea69d06c58..356b3997583f 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h @@ -107,7 +107,7 @@ #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" #define RT_USING_CONSOLE_OUTPUT_CTL -#define RT_VER_NUM 0x50300 +#define RT_VER_NUM 0x50400 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define RT_USING_HW_ATOMIC @@ -253,6 +253,9 @@ /* LVGL: powerful and easy-to-use embedded GUI library */ + +/* GD32EmbeddedUI demos require LVGL v8.3.11 */ + /* end of LVGL: powerful and easy-to-use embedded GUI library */ /* u8g2: a monochrome graphic library */ @@ -299,6 +302,10 @@ /* end of Kendryte SDK */ +/* MM32 HAL & SDK Drivers */ + +/* end of MM32 HAL & SDK Drivers */ + /* WCH HAL & SDK Drivers */ /* end of WCH HAL & SDK Drivers */ @@ -329,9 +336,21 @@ /* end of HPMicro SDK */ +/* FM33 Drivers */ + +/* end of FM33 Drivers */ + /* FT32 HAL & SDK Drivers */ /* end of FT32 HAL & SDK Drivers */ + +/* NOVOSNS Drivers */ + +/* end of NOVOSNS Drivers */ + +/* N32 Drivers */ + +/* end of N32 Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.py b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.py index ab1be162d20f..34daf965cd37 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.py +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.py @@ -29,11 +29,11 @@ if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') -BUILD = 'debug' -# BUILD = 'release' +# BUILD = 'debug' +BUILD = 'release' # Read linker script selection from rtconfig.h (set by Kconfig BSP_LINKER_SCRIPT_* choice). -# Supported types: RAM, FLEXSPI_NOR, FLEXSPI_NOR_HYPERRAM +# Supported types: RAM, RAM_INDUSTRY, FLEXSPI_NOR, FLEXSPI_NOR_HYPERRAM # Default to RAM when no match is found. _LINKER_SCRIPT_TYPE = 'RAM' _rtconfig_h = os.path.join(os.path.dirname(__file__), 'rtconfig.h') @@ -50,6 +50,9 @@ if _s.startswith('#define BSP_LINKER_SCRIPT_FLEXSPI_NOR'): _LINKER_SCRIPT_TYPE = 'FLEXSPI_NOR' break + if _s.startswith('#define BSP_LINKER_SCRIPT_RAM_INDUSTRY'): + _LINKER_SCRIPT_TYPE = 'RAM_INDUSTRY' + break if _s.startswith('#define BSP_LINKER_SCRIPT_RAM'): _LINKER_SCRIPT_TYPE = 'RAM' break @@ -57,6 +60,7 @@ # Base filename (without extension) for the selected linker script. _LINKER_SCRIPT_BASE = { 'RAM': 'MIMXRT1189xxxxx_cm33_ram', + 'RAM_INDUSTRY': 'MIMXRT1189xxxxx_cm33_ram_industry', 'FLEXSPI_NOR': 'MIMXRT1189xxxxx_cm33_flexspi_nor', 'FLEXSPI_NOR_HYPERRAM': 'MIMXRT1189xxxxx_cm33_flexspi_nor_hyperram', }[_LINKER_SCRIPT_TYPE] @@ -232,6 +236,7 @@ # Map from linker script type to the matching Keil target name. _LINKER_SCRIPT_TO_KEIL_TARGET = { 'RAM': 'rtthread_ram', + 'RAM_INDUSTRY': 'rtthread_ram_industry', 'FLEXSPI_NOR': 'rtthread_flexspi_nor', 'FLEXSPI_NOR_HYPERRAM': 'rtthread_flexspi_nor_hyperram', } @@ -248,6 +253,10 @@ def update_keil_active_target(uvoptx_path='project.uvoptx'): tree = etree.parse(uvoptx_path) root = tree.getroot() + if not any(tgt.findtext('TargetName') == active for tgt in tree.findall('Target')): + print('Keil target not found: ' + active + '; active target unchanged') + return + for tgt in tree.findall('Target'): tname = tgt.find('TargetName') is_current = tgt.find('TargetOption/OPTFL/IsCurrentTarget') diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.ewd b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.ewd index 7d85c610659e..f7d5f198f7fe 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.ewd +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.ewd @@ -1640,6 +1640,1645 @@ 0 + + rtthread_ram_industry + + ARM + + 0 + + C-SPY + 2 + + 33 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + E2_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + GPLINK_ID + 2 + + 0 + 1 + 0 + + + + + + + IJET_ID + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 3 + 1 + 0 + + + + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\Azure\AzureArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9a.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + rtthread_flexspi_nor diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.ewp b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.ewp index 202125caf683..0e0e92f00542 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.ewp +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.ewp @@ -1099,6 +1099,1104 @@ 2 + + rtthread_ram_industry + + ARM + + 0 + + General + 3 + + 37 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + rtthread_flexspi_nor diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.uvoptx b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.uvoptx index 9d840ecb20b4..b67deb530d67 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.uvoptx +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.uvoptx @@ -181,6 +181,166 @@ + + rtthread_ram_industry + 0x4 + ARM-ADS + + 33000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 0 + + 8 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + .\evkmimxrt1180_ram_cm33.ini + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U600109563 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(5BA02477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD30500000 -FC8000 -FN1 -FF0MIMXRT1180_EVK_FSPI1_QSPI_CM33.FMIMXRT1180_EVK_FSPI1_QSPI_CM33 -FS028000000 -FL01000000 -FP0($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM33.FLM) + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC20000 -FN2 -FF0MIMXRT1180_EVK_FSPI1_QSPI_CM33 -FS028000000 -FL01000000 -FF1MIMXRT1180_EVK_FSPI1_QSPI_CM7 -FS128000000 -FL11000000 -FP0($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM33.FLM) -FP1($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + + rtthread_flexspi_nor 0x4 diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.uvprojx b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.uvprojx index 953b5687c1fb..d88da827e11e 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.uvprojx +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.uvprojx @@ -381,6 +381,381 @@ + + rtthread_ram_industry + 0x4 + ARM-ADS + 6220000::V6.22::ARMCLANG + 1 + + + MIMXRT1189CVM8C:cm33 + NXP + NXP.MIMXRT1189_DFP.25.06.00 + https://mcuxpresso.nxp.com/cmsis_pack/repo/ + CPUTYPE("Cortex-M33") FPU3(SFPU) TZ DSP ELITTLE + + + + 0 + $$Device:MIMXRT1189CVM8B$fsl_device_registers.h + + + + + + + + + + $$Device:MIMXRT1189CVM8B$MIMXRT1189_cm33.xml + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 1 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMV8M.DLL + -REMAP -MPU + DCM.DLL + -pCM33 + SARMV8M.DLL + -MPU + TCM.DLL + -pCM33 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 0 + 1 + 4102 + + 1 + BIN\UL2V8M.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + "Cortex-M33" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x100000 + + + 1 + 0x0 + 0x20000 + + + 1 + 0x8000000 + 0x1000000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x20000 + + + 0 + 0x20240000 + 0x80000 + + + 0 + 0x202c0000 + 0x80000 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x1ffe0000 + 0x20000 + + + + + + 1 + 6 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + -fno-common -fdata-sections -fno-builtin -mthumb + + + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + -x assembler-with-cpp + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\board\linker_scripts\MIMXRT1189xxxxx_cm33_ram_industry.scf + + + + + 6439,6314 + + + + rtthread_flexspi_nor 0x4 diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.config b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.config index 33552fce3a47..dfcddb5ea790 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.config +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.config @@ -182,7 +182,7 @@ CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart12" CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y -CONFIG_RT_VER_NUM=0x50300 +CONFIG_RT_VER_NUM=0x50400 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel @@ -471,6 +471,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ABUP_FOTA is not set # CONFIG_PKG_USING_LIBCURL2RTT is not set # CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_ERPC is not set # CONFIG_PKG_USING_AGILE_TELNET is not set # CONFIG_PKG_USING_NMEALIB is not set # CONFIG_PKG_USING_PDULIB is not set @@ -557,6 +558,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_LVGL is not set # CONFIG_PKG_USING_LV_MUSIC_DEMO is not set # CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# GD32EmbeddedUI demos require LVGL v8.3.11 +# # end of LVGL: powerful and easy-to-use embedded GUI library # @@ -587,12 +592,15 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_PERSIMMON is not set # CONFIG_PKG_USING_3GPP_AMRNB is not set +# CONFIG_PKG_USING_LITETYPE is not set # end of multimedia packages # # tools packages # # CONFIG_PKG_USING_VECTOR is not set +# CONFIG_PKG_USING_SORCH is not set +# CONFIG_PKG_USING_DICT is not set # CONFIG_PKG_USING_CMBACKTRACE is not set # CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set @@ -645,6 +653,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UORB is not set # CONFIG_PKG_USING_RT_TUNNEL is not set # CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# CONFIG_PKG_USING_FEE is not set +# CONFIG_PKG_USING_MRAMTRACE is not set # end of tools packages # @@ -740,6 +750,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_HEARTBEAT is not set # CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set # CONFIG_PKG_USING_CHERRYECAT is not set +# CONFIG_PKG_USING_EVENT_LOOP is not set +# CONFIG_PKG_USING_THREAD_MANAGER is not set # end of system packages # @@ -791,6 +803,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set # CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set # CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32N6_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32N657xx_FSBL is not set # end of STM32 HAL & SDK Drivers # @@ -823,7 +838,21 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set -# CONFIG_PKG_USING_MM32 is not set + +# +# MM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_MM32F103XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F3270X_CMSIS is not set +# CONFIG_PKG_USING_MM32F5260X_CMSIS is not set +# CONFIG_PKG_USING_MM32L0XX_CMSIS is not set +# CONFIG_PKG_USING_MM32L3XX_CMSIS is not set +# CONFIG_PKG_USING_MM32F103XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F3270X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32F5260X_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L0XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_MM32L3XX_HAL_DRIVER is not set +# end of MM32 HAL & SDK Drivers # # WCH HAL & SDK Drivers @@ -888,9 +917,7 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" # # NUVOTON Drivers # -# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set # CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set -# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set # end of NUVOTON Drivers # @@ -908,6 +935,12 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" # CONFIG_PKG_USING_HPM_SDK is not set # end of HPMicro SDK +# +# FM33 Drivers +# +# CONFIG_PKG_USING_FM33LG0XX_FL_LIBRARY is not set +# end of FM33 Drivers + # # FT32 HAL & SDK Drivers # @@ -916,6 +949,23 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" # CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set # CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set # end of FT32 HAL & SDK Drivers + +# +# NOVOSNS Drivers +# +# CONFIG_PKG_USING_NOVOSNS_SERIES_DRIVER is not set +# end of NOVOSNS Drivers + +# +# N32 Drivers +# +# CONFIG_PKG_USING_N32H7XX_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H7XX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H49X_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_STD_DRIVER is not set +# CONFIG_PKG_USING_N32H47X_48X_CMSIS_DRIVER is not set +# end of N32 Drivers # end of HAL & SDK Drivers # @@ -995,6 +1045,7 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" # CONFIG_PKG_USING_QMI8658 is not set # CONFIG_PKG_USING_ICM20948 is not set # CONFIG_PKG_USING_SCD4X is not set +# CONFIG_PKG_USING_BMI270 is not set # end of sensors drivers # @@ -1049,6 +1100,7 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" # CONFIG_PKG_USING_WK2124 is not set # CONFIG_PKG_USING_LY68L6400 is not set # CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_CH390 is not set # CONFIG_PKG_USING_SSD1306 is not set # CONFIG_PKG_USING_QKEY is not set # CONFIG_PKG_USING_RS485 is not set @@ -1096,8 +1148,10 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" # CONFIG_PKG_USING_ISOTP_C is not set # CONFIG_PKG_USING_IKUNLED is not set # CONFIG_PKG_USING_INS5T8025 is not set +# CONFIG_PKG_USING_IRUART is not set # CONFIG_PKG_USING_ST7305 is not set # CONFIG_PKG_USING_TM1668 is not set +# CONFIG_PKG_USING_TCA9548A is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1115,6 +1169,9 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" # CONFIG_PKG_USING_NAXOS is not set # CONFIG_PKG_USING_R_TINYMAIX is not set # CONFIG_PKG_USING_LLMCHAT is not set +# CONFIG_PKG_USING_LIME_TM is not set +# CONFIG_PKG_USING_AIFES is not set +# CONFIG_PKG_USING_AGENT is not set # end of AI packages # @@ -1174,6 +1231,8 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_CANOPENNODE is not set +# CONFIG_PKG_USING_LELY is not set # CONFIG_PKG_USING_ZLIB is not set # CONFIG_PKG_USING_MINIZIP is not set # CONFIG_PKG_USING_HEATSHRINK is not set @@ -1199,6 +1258,8 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" # CONFIG_PKG_USING_QPARAM is not set # CONFIG_PKG_USING_CorevMCU_CLI is not set # CONFIG_PKG_USING_DRMP is not set +# CONFIG_PKG_USING_AUTOGEN_PARAMETER_MANAGER is not set +# CONFIG_PKG_USING_SIMULATED_SENSOR is not set # end of miscellaneous packages # @@ -1495,7 +1556,9 @@ CONFIG_BSP_LPUART12_TX_DMA_CHANNEL=23 # Board extended module Drivers # # CONFIG_BSP_LINKER_SCRIPT_RAM is not set +# CONFIG_BSP_LINKER_SCRIPT_RAM_INDUSTRY is not set # CONFIG_BSP_LINKER_SCRIPT_HYPERRAM is not set CONFIG_BSP_LINKER_SCRIPT_FLEXSPI_NOR=y # CONFIG_BSP_LINKER_SCRIPT_FLEXSPI_NOR_HYPERRAM is not set +# CONFIG_BSP_LINKER_SCRIPT_FLEXSPI_NOR_INDUSTRY is not set # end of Hardware Drivers Config diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/Kconfig b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/Kconfig index cdf8842e5a06..f9127fada66b 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/Kconfig +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/Kconfig @@ -821,6 +821,17 @@ choice help Link the image to run entirely from internal SRAM. + config BSP_LINKER_SCRIPT_RAM_INDUSTRY + bool "RAM - Industrial Ethernet (512KB TCM + 512KB OCRAM1 + 96KB OCRAM2 + 32KB shared memory)" + help + Link the image to run from internal SRAM for industrial Ethernet + development. CM7 uses 256KB ITCM and 256KB DTCM, all accessible + OCRAM1 (496KB; the first 16KB is blocked by TRDC), and 96KB OCRAM2 + exclusively. The last 32KB OCRAM2 is shared with CM33 and must + match the CM33 industry layout. The GCC linker script (.ld), + ARMCLANG scatter file (.scf) and IAR configuration file (.icf) + are provided. + config BSP_LINKER_SCRIPT_HYPERRAM bool "HyperRAM (internal SRAM + external HyperRAM)" help @@ -837,6 +848,15 @@ choice help Link the image to XIP from external NOR flash and use HyperRAM as additional RAM. + + config BSP_LINKER_SCRIPT_FLEXSPI_NOR_INDUSTRY + bool "FlexSPI NOR Flash - Industrial Ethernet (XIP + 512KB OCRAM1 + 96KB OCRAM2 + 32KB shared memory)" + help + Link the image to XIP from external NOR flash for industrial + Ethernet development. CM7 uses the whole OCRAM1, 96KB OCRAM2 + exclusively and shares 32KB OCRAM2 with CM33. The GCC linker + script (.ld), the ARMCLANG scatter file (.scf) and the IAR linker + configuration file (.icf) are provided. endchoice endmenu diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/SConscript index f9fa157f1ada..ca6e0cb6ed06 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/SConscript +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/SConscript @@ -86,8 +86,11 @@ if GetDepend(['RT_USING_CHERRYUSB']): if GetDepend(['BSP_LINKER_SCRIPT_FLEXSPI_NOR']): CPPDEFINES += ['XIP_EXTERNAL_FLASH=1'] +if GetDepend(['BSP_LINKER_SCRIPT_FLEXSPI_NOR_INDUSTRY']): + CPPDEFINES += ['XIP_EXTERNAL_FLASH=1'] + if GetDepend(['BSP_LINKER_SCRIPT_FLEXSPI_NOR_HYPERRAM']): - CPPDEFINES += ['XIP_EXTERNAL_FLASH=1'] + CPPDEFINES += ['XIP_EXTERNAL_FLASH=1'] group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES, LINKFLAGS=LINKFLAGS) diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.c index c7f63b79af6d..4595df1bc639 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.c @@ -1256,8 +1256,8 @@ void PHY_Reset(void) void rt_hw_board_init() { - BOARD_CommonSetting(); BOARD_ConfigMPU(); + BOARD_CommonSetting(); BOARD_InitBootPins(); BOARD_BootClockRUN(); diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor.icf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor.icf index 9741eea988aa..0c079ab3bba2 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor.icf +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor.icf @@ -1,153 +1,153 @@ -/* -** ################################################################### -** Processors: MIMXRT1189CVM8B_cm7 -** MIMXRT1189CVM8C_cm7 -** MIMXRT1189XVM8B_cm7 -** MIMXRT1189XVM8C_cm7 -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: IMXRT1180RM, Rev 5, 01/2024 -** Version: rev. 2.0, 2024-01-18 -** Build: b250310 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2025 NXP -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -/* Board memory map */ -define symbol m_itcm_start = 0x00000000; -define symbol m_itcm_size = 0x00040000; - -define symbol m_dtcm_start = 0x20000000; -define symbol m_dtcm_size = 0x00040000; - -define symbol m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */ -define symbol m_ocram1_size = 0x0007C000; - -define symbol m_ocram2_start = 0x20500000; -define symbol m_ocram2_size = 0x00040000; - -define symbol m_sdram_start = 0x80000000; -define symbol m_sdram_size = 0x01E00000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ -define symbol m_hyperram_start = 0x04000000; -define symbol m_hyperram_size = 0x00600000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ -define symbol m_flash_start = 0x28800000; -define symbol m_flash_size = 0x00800000; - -/* General definition */ -define symbol app_image_offset = 0x00000000; -define symbol vector_table_size = 0x00000400; -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x1000; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x8000; -} - -define symbol m_qacode_start = m_itcm_start + (isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0); -define symbol m_qacode_end = m_itcm_start + m_itcm_size - 1; -define symbol m_qadata_start = m_dtcm_start; -define symbol m_qadata_end = m_dtcm_start + m_dtcm_size - 1; -define symbol m_ram_vector_table_start = m_itcm_start; - -/* Target specific definition, code & data allocation */ -define symbol m_code_size = m_flash_size - app_image_offset; -define symbol m_data_size = m_dtcm_size; -define symbol m_ncache_size = isdefinedsymbol(__multicore__) ? 0x20000 : 0x40000; /* m_ncache_size must be 2^N */ -define symbol m_shmem_size = m_ocram2_size; /* m_shmem_size must be 2^N */ - -define symbol m_ocram1_size_for_cm7 = isdefinedsymbol(__multicore__) ? 0x40000 : m_ocram1_size; - -define symbol m_ram_vector_table_size = isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0; - -define symbol m_text_start = m_flash_start + app_image_offset; -define symbol m_text_end = m_text_start + m_code_size - 1; -define symbol m_interrupts_start = m_text_start; - -define symbol m_data_start = m_dtcm_start; -define symbol m_data_end = m_data_start + m_data_size - 1; - -define symbol m_ncache_start = m_ocram1_start + m_ocram1_size - m_ncache_size; /* (m_ncache_start % m_ncache_size) must be 0 */ -define symbol m_ncache_end = m_ncache_start + m_ncache_size - 1; - -define symbol m_heap_start = m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7; -define symbol m_heap_end = m_ncache_start - 1; - -if (isdefinedsymbol(__use_shmem__)) { - define symbol m_rpmsg_sh_mem_start = m_ocram2_start; /* (m_rpmsg_sh_mem_start % m_shmem_size) must be 0 */ - define symbol m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; -} - -/* Exported symbol definition */ -define exported symbol __VECTOR_TABLE = m_interrupts_start; -define exported symbol __VECTOR_RAM = m_ram_vector_table_start; -define exported symbol __RAM_VECTOR_TABLE_SIZE = m_ram_vector_table_size; -define exported symbol __NCACHE_REGION_START = m_ncache_start; -define exported symbol __NCACHE_REGION_SIZE = m_ncache_end - m_ncache_start + 1; -if (isdefinedsymbol(__use_shmem__)) { - define exported symbol rpmsg_sh_mem_start = m_rpmsg_sh_mem_start; - define exported symbol rpmsg_sh_mem_end = m_rpmsg_sh_mem_end; - define exported symbol __RPMSG_SH_MEM_START = m_rpmsg_sh_mem_start; - define exported symbol __RPMSG_SH_MEM_SIZE = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1; -} - -/* Region definition */ -define memory mem with size = 4G; -define region TEXT_region = mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; -define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; -define region HEAP_region = mem:[from m_heap_start to m_heap_end]; -define region QACODE_region = mem:[from m_qacode_start to m_qacode_end]; -define region QADATA_region = mem:[from m_qadata_start to m_qadata_end]; -if (isdefinedsymbol(__use_shmem__)) { - define region rpmsg_sh_mem_region = mem:[from m_rpmsg_sh_mem_start to m_rpmsg_sh_mem_end]; -} - -/* Block definition */ -define block RW { readwrite }; -define block ZI { zi }; -define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; -define block QACCESS_CODE { section CodeQuickAccess }; -define block QACCESS_DATA { section DataQuickAccess }; -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; - -initialize by copy { readwrite, section .textrw, section DataQuickAccess, section CodeQuickAccess, - ro code object fsl_flexspi.o, ro code object drv_flexspi_nor_flash.o, ro code object drv_flexspi.o }; -do not initialize { section .noinit }; -if (isdefinedsymbol(__use_shmem__)) { - do not initialize { section rpmsg_sh_mem_section }; -} - -place at address mem: m_interrupts_start { readonly section .intvec }; - -place in TEXT_region { readonly }; -place in QACODE_region { block QACCESS_CODE }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { block QACCESS_DATA }; -place in NCACHE_region { block NCACHE_VAR }; -place in CSTACK_region { block CSTACK }; -if (isdefinedsymbol(__heap_noncacheable__)) { - place in NCACHE_region { last block HEAP }; -} else { - place in HEAP_region { last block HEAP }; -} -if (isdefinedsymbol(__use_shmem__)) { - place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; -} +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm7 +** MIMXRT1189CVM8C_cm7 +** MIMXRT1189XVM8B_cm7 +** MIMXRT1189XVM8C_cm7 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Board memory map */ +define symbol m_itcm_start = 0x00000000; +define symbol m_itcm_size = 0x00040000; + +define symbol m_dtcm_start = 0x20000000; +define symbol m_dtcm_size = 0x00040000; + +define symbol m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */ +define symbol m_ocram1_size = 0x0007C000; + +define symbol m_ocram2_start = 0x20500000; +define symbol m_ocram2_size = 0x00040000; + +define symbol m_sdram_start = 0x80000000; +define symbol m_sdram_size = 0x01E00000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +define symbol m_hyperram_start = 0x04000000; +define symbol m_hyperram_size = 0x00600000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +define symbol m_flash_start = 0x28800000; +define symbol m_flash_size = 0x00800000; + +/* General definition */ +define symbol app_image_offset = 0x00000000; +define symbol vector_table_size = 0x00000400; +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x1000; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x8000; +} + +define symbol m_qacode_start = m_itcm_start + (isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0); +define symbol m_qacode_end = m_itcm_start + m_itcm_size - 1; +define symbol m_qadata_start = m_dtcm_start; +define symbol m_qadata_end = m_dtcm_start + m_dtcm_size - 1; +define symbol m_ram_vector_table_start = m_itcm_start; + +/* Target specific definition, code & data allocation */ +define symbol m_code_size = m_flash_size - app_image_offset; +define symbol m_data_size = m_dtcm_size; +define symbol m_ncache_size = isdefinedsymbol(__multicore__) ? 0x20000 : 0x40000; /* m_ncache_size must be 2^N */ +define symbol m_shmem_size = m_ocram2_size; /* m_shmem_size must be 2^N */ + +define symbol m_ocram1_size_for_cm7 = isdefinedsymbol(__multicore__) ? 0x40000 : m_ocram1_size; + +define symbol m_ram_vector_table_size = isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0; + +define symbol m_text_start = m_flash_start + app_image_offset; +define symbol m_text_end = m_text_start + m_code_size - 1; +define symbol m_interrupts_start = m_text_start; + +define symbol m_data_start = m_dtcm_start; +define symbol m_data_end = m_data_start + m_data_size - 1; + +define symbol m_ncache_start = m_ocram1_start + m_ocram1_size - m_ncache_size; /* (m_ncache_start % m_ncache_size) must be 0 */ +define symbol m_ncache_end = m_ncache_start + m_ncache_size - 1; + +define symbol m_heap_start = m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7; +define symbol m_heap_end = m_ncache_start - 1; + +if (isdefinedsymbol(__use_shmem__)) { + define symbol m_rpmsg_sh_mem_start = m_ocram2_start; /* (m_rpmsg_sh_mem_start % m_shmem_size) must be 0 */ + define symbol m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; +} + +/* Exported symbol definition */ +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_ram_vector_table_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = m_ram_vector_table_size; +define exported symbol __NCACHE_REGION_START = m_ncache_start; +define exported symbol __NCACHE_REGION_SIZE = m_ncache_end - m_ncache_start + 1; +if (isdefinedsymbol(__use_shmem__)) { + define exported symbol rpmsg_sh_mem_start = m_rpmsg_sh_mem_start; + define exported symbol rpmsg_sh_mem_end = m_rpmsg_sh_mem_end; + define exported symbol __RPMSG_SH_MEM_START = m_rpmsg_sh_mem_start; + define exported symbol __RPMSG_SH_MEM_SIZE = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1; +} + +/* Region definition */ +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; +define region HEAP_region = mem:[from m_heap_start to m_heap_end]; +define region QACODE_region = mem:[from m_qacode_start to m_qacode_end]; +define region QADATA_region = mem:[from m_qadata_start to m_qadata_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from m_rpmsg_sh_mem_start to m_rpmsg_sh_mem_end]; +} + +/* Block definition */ +define block RW { readwrite }; +define block ZI { zi }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; +define block QACCESS_CODE { section CodeQuickAccess }; +define block QACCESS_DATA { section DataQuickAccess }; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; + +initialize by copy { readwrite, section .textrw, section DataQuickAccess, section CodeQuickAccess, + ro code object fsl_flexspi.o, ro code object drv_flexspi_nor_flash.o, ro code object drv_flexspi.o }; +do not initialize { section .noinit }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place in TEXT_region { readonly }; +place in QACODE_region { block QACCESS_CODE }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { block QACCESS_DATA }; +place in NCACHE_region { block NCACHE_VAR }; +place in CSTACK_region { block CSTACK }; +if (isdefinedsymbol(__heap_noncacheable__)) { + place in NCACHE_region { last block HEAP }; +} else { + place in HEAP_region { last block HEAP }; +} +if (isdefinedsymbol(__use_shmem__)) { + place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor.ld b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor.ld index e62c0c9bcf86..f4a103f7f334 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor.ld +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor.ld @@ -131,8 +131,8 @@ SECTIONS .text : { . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ + *(EXCLUDE_FILE(*fsl_flexspi.o *drv_flexspi_nor_flash.o *drv_flexspi.o) .text) + *(EXCLUDE_FILE(*fsl_flexspi.o *drv_flexspi_nor_flash.o *drv_flexspi.o) .text*) *(.rodata) /* .rodata sections (constants, strings, etc.) */ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ *(.glue_7) /* glue arm to thumb code */ @@ -252,6 +252,11 @@ SECTIONS . = ALIGN(32); __ram_function_start__ = .; *(CodeQuickAccess) + /* The FlexSPI drivers must run from TCM while the flash is being + reconfigured, mirroring the Keil/IAR QuickAccess placement. */ + *fsl_flexspi.o(.text*) + *drv_flexspi_nor_flash.o(.text*) + *drv_flexspi.o(.text*) . = ALIGN(128); __ram_function_end__ = .; } > m_qacode diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_hyperram.icf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_hyperram.icf index 6867ac591025..07dba1801bc1 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_hyperram.icf +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_hyperram.icf @@ -1,157 +1,157 @@ -/* -** ################################################################### -** Processors: MIMXRT1189CVM8B_cm7 -** MIMXRT1189CVM8C_cm7 -** MIMXRT1189XVM8B_cm7 -** MIMXRT1189XVM8C_cm7 -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: IMXRT1180RM, Rev 5, 01/2024 -** Version: rev. 2.0, 2024-01-18 -** Build: b250310 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2025 NXP -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -/* Board memory map */ -define symbol m_itcm_start = 0x00000000; -define symbol m_itcm_size = 0x00040000; - -define symbol m_dtcm_start = 0x20000000; -define symbol m_dtcm_size = 0x00040000; - -define symbol m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */ -define symbol m_ocram1_size = 0x0007C000; - -define symbol m_ocram2_start = 0x20500000; -define symbol m_ocram2_size = 0x00040000; - -define symbol m_sdram_start = 0x80000000; -define symbol m_sdram_size = 0x01E00000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ -define symbol m_hyperram_start = 0x04000000; -define symbol m_hyperram_size = 0x00600000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ -define symbol m_flash_start = 0x28800000; -define symbol m_flash_size = 0x00800000; - -/* General definition */ -define symbol app_image_offset = 0x00000000; -define symbol vector_table_size = 0x00000400; -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x1000; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x8000; -} - -define symbol m_qacode_start = m_itcm_start + (isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0); -define symbol m_qacode_end = m_itcm_start + m_itcm_size - 1; -define symbol m_qadata_start = m_dtcm_start; -define symbol m_qadata_end = m_dtcm_start + m_dtcm_size - 1; -define symbol m_ram_vector_table_start = m_itcm_start; - -/* Target specific definition, code & data allocation */ -define symbol m_code_size = m_flash_size - app_image_offset; -define symbol m_data_size = 0x00600000; -define symbol m_ncache_size = isdefinedsymbol(__multicore__) ? 0x20000 : 0x40000; /* m_ncache_size must be 2^N */ -define symbol m_shmem_size = m_ocram2_size; /* m_shmem_size must be 2^N */ - -define symbol m_ocram1_size_for_cm7 = isdefinedsymbol(__multicore__) ? 0x40000 : m_ocram1_size; - -define symbol m_ram_vector_table_size = isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0; - -define symbol m_text_start = m_flash_start + app_image_offset; -define symbol m_text_end = m_text_start + m_code_size - 1; -define symbol m_interrupts_start = m_text_start; - -define symbol m_data_start = m_hyperram_start; -define symbol m_data_end = m_data_start + m_data_size - 1; - -define symbol m_ncache_start = m_ocram1_start + m_ocram1_size - m_ncache_size; /* (m_ncache_start % m_ncache_size) must be 0 */ -define symbol m_ncache_end = m_ncache_start + m_ncache_size - 1; - -define symbol m_heap_start = m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7; -define symbol m_heap_end = m_ncache_start - 1; - -if (isdefinedsymbol(__use_shmem__)) { - define symbol m_rpmsg_sh_mem_start = m_ocram2_start; /* (m_rpmsg_sh_mem_start % m_shmem_size) must be 0 */ - define symbol m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; -} - -/* Exported symbol definition */ -define exported symbol __VECTOR_TABLE = m_interrupts_start; -define exported symbol __VECTOR_RAM = m_ram_vector_table_start; -define exported symbol __RAM_VECTOR_TABLE_SIZE = m_ram_vector_table_size; -define exported symbol __NCACHE_REGION_START = m_ncache_start; -define exported symbol __NCACHE_REGION_SIZE = m_ncache_end - m_ncache_start + 1; -if (isdefinedsymbol(__use_shmem__)) { - define exported symbol rpmsg_sh_mem_start = m_rpmsg_sh_mem_start; - define exported symbol rpmsg_sh_mem_end = m_rpmsg_sh_mem_end; - define exported symbol __RPMSG_SH_MEM_START = m_rpmsg_sh_mem_start; - define exported symbol __RPMSG_SH_MEM_SIZE = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1; -} - -/* Region definition */ -define memory mem with size = 4G; -define region TEXT_region = mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; -define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; -define region HEAP_region = mem:[from m_heap_start to m_heap_end]; -define region QACODE_region = mem:[from m_qacode_start to m_qacode_end]; -define region QADATA_region = mem:[from m_qadata_start to m_qadata_end]; -if (isdefinedsymbol(__use_shmem__)) { - define region rpmsg_sh_mem_region = mem:[from m_rpmsg_sh_mem_start to m_rpmsg_sh_mem_end]; -} - -/* Block definition */ -define block RW { readwrite }; -define block ZI { zi }; -define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; -define block QACCESS_CODE { section CodeQuickAccess }; -define block QACCESS_DATA { section DataQuickAccess }; -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; - -/* cache line size = 32 bytes */ -define block CACHE_LINE_DATA_ZI with alignment = 32, end alignment = 32 { section CacheLineData }; -define block CACHE_LINE_DATA_RW with alignment = 32, end alignment = 32 { section CacheLineData.init }; - -initialize by copy { readwrite, section .textrw, section DataQuickAccess, section CodeQuickAccess, - ro code object fsl_flexspi.o, ro code object drv_flexspi_nor_flash.o, ro code object drv_flexspi.o }; -do not initialize { section .noinit }; -if (isdefinedsymbol(__use_shmem__)) { - do not initialize { section rpmsg_sh_mem_section }; -} - -place at address mem: m_interrupts_start { readonly section .intvec }; - -place in TEXT_region { readonly }; -place in QACODE_region { block QACCESS_CODE }; -place in DATA_region { block RW, block CACHE_LINE_DATA_RW }; -place in DATA_region { block ZI, block CACHE_LINE_DATA_ZI }; -place in QADATA_region { block QACCESS_DATA }; -place in NCACHE_region { block NCACHE_VAR }; -place in CSTACK_region { block CSTACK }; -if (isdefinedsymbol(__heap_noncacheable__)) { - place in NCACHE_region { last block HEAP }; -} else { - place in HEAP_region { last block HEAP }; -} -if (isdefinedsymbol(__use_shmem__)) { - place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; -} +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm7 +** MIMXRT1189CVM8C_cm7 +** MIMXRT1189XVM8B_cm7 +** MIMXRT1189XVM8C_cm7 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Board memory map */ +define symbol m_itcm_start = 0x00000000; +define symbol m_itcm_size = 0x00040000; + +define symbol m_dtcm_start = 0x20000000; +define symbol m_dtcm_size = 0x00040000; + +define symbol m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */ +define symbol m_ocram1_size = 0x0007C000; + +define symbol m_ocram2_start = 0x20500000; +define symbol m_ocram2_size = 0x00040000; + +define symbol m_sdram_start = 0x80000000; +define symbol m_sdram_size = 0x01E00000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +define symbol m_hyperram_start = 0x04000000; +define symbol m_hyperram_size = 0x00600000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +define symbol m_flash_start = 0x28800000; +define symbol m_flash_size = 0x00800000; + +/* General definition */ +define symbol app_image_offset = 0x00000000; +define symbol vector_table_size = 0x00000400; +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x1000; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x8000; +} + +define symbol m_qacode_start = m_itcm_start + (isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0); +define symbol m_qacode_end = m_itcm_start + m_itcm_size - 1; +define symbol m_qadata_start = m_dtcm_start; +define symbol m_qadata_end = m_dtcm_start + m_dtcm_size - 1; +define symbol m_ram_vector_table_start = m_itcm_start; + +/* Target specific definition, code & data allocation */ +define symbol m_code_size = m_flash_size - app_image_offset; +define symbol m_data_size = 0x00600000; +define symbol m_ncache_size = isdefinedsymbol(__multicore__) ? 0x20000 : 0x40000; /* m_ncache_size must be 2^N */ +define symbol m_shmem_size = m_ocram2_size; /* m_shmem_size must be 2^N */ + +define symbol m_ocram1_size_for_cm7 = isdefinedsymbol(__multicore__) ? 0x40000 : m_ocram1_size; + +define symbol m_ram_vector_table_size = isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0; + +define symbol m_text_start = m_flash_start + app_image_offset; +define symbol m_text_end = m_text_start + m_code_size - 1; +define symbol m_interrupts_start = m_text_start; + +define symbol m_data_start = m_hyperram_start; +define symbol m_data_end = m_data_start + m_data_size - 1; + +define symbol m_ncache_start = m_ocram1_start + m_ocram1_size - m_ncache_size; /* (m_ncache_start % m_ncache_size) must be 0 */ +define symbol m_ncache_end = m_ncache_start + m_ncache_size - 1; + +define symbol m_heap_start = m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7; +define symbol m_heap_end = m_ncache_start - 1; + +if (isdefinedsymbol(__use_shmem__)) { + define symbol m_rpmsg_sh_mem_start = m_ocram2_start; /* (m_rpmsg_sh_mem_start % m_shmem_size) must be 0 */ + define symbol m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; +} + +/* Exported symbol definition */ +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_ram_vector_table_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = m_ram_vector_table_size; +define exported symbol __NCACHE_REGION_START = m_ncache_start; +define exported symbol __NCACHE_REGION_SIZE = m_ncache_end - m_ncache_start + 1; +if (isdefinedsymbol(__use_shmem__)) { + define exported symbol rpmsg_sh_mem_start = m_rpmsg_sh_mem_start; + define exported symbol rpmsg_sh_mem_end = m_rpmsg_sh_mem_end; + define exported symbol __RPMSG_SH_MEM_START = m_rpmsg_sh_mem_start; + define exported symbol __RPMSG_SH_MEM_SIZE = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1; +} + +/* Region definition */ +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; +define region HEAP_region = mem:[from m_heap_start to m_heap_end]; +define region QACODE_region = mem:[from m_qacode_start to m_qacode_end]; +define region QADATA_region = mem:[from m_qadata_start to m_qadata_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from m_rpmsg_sh_mem_start to m_rpmsg_sh_mem_end]; +} + +/* Block definition */ +define block RW { readwrite }; +define block ZI { zi }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; +define block QACCESS_CODE { section CodeQuickAccess }; +define block QACCESS_DATA { section DataQuickAccess }; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; + +/* cache line size = 32 bytes */ +define block CACHE_LINE_DATA_ZI with alignment = 32, end alignment = 32 { section CacheLineData }; +define block CACHE_LINE_DATA_RW with alignment = 32, end alignment = 32 { section CacheLineData.init }; + +initialize by copy { readwrite, section .textrw, section DataQuickAccess, section CodeQuickAccess, + ro code object fsl_flexspi.o, ro code object drv_flexspi_nor_flash.o, ro code object drv_flexspi.o }; +do not initialize { section .noinit }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place in TEXT_region { readonly }; +place in QACODE_region { block QACCESS_CODE }; +place in DATA_region { block RW, block CACHE_LINE_DATA_RW }; +place in DATA_region { block ZI, block CACHE_LINE_DATA_ZI }; +place in QADATA_region { block QACCESS_DATA }; +place in NCACHE_region { block NCACHE_VAR }; +place in CSTACK_region { block CSTACK }; +if (isdefinedsymbol(__heap_noncacheable__)) { + place in NCACHE_region { last block HEAP }; +} else { + place in HEAP_region { last block HEAP }; +} +if (isdefinedsymbol(__use_shmem__)) { + place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_hyperram.ld b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_hyperram.ld index c1a7b3648dd8..d19405bee9af 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_hyperram.ld +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_hyperram.ld @@ -131,8 +131,8 @@ SECTIONS .text : { . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ + *(EXCLUDE_FILE(*fsl_flexspi.o *drv_flexspi_nor_flash.o *drv_flexspi.o) .text) + *(EXCLUDE_FILE(*fsl_flexspi.o *drv_flexspi_nor_flash.o *drv_flexspi.o) .text*) *(.rodata) /* .rodata sections (constants, strings, etc.) */ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ *(.glue_7) /* glue arm to thumb code */ @@ -253,6 +253,11 @@ SECTIONS . = ALIGN(32); __ram_function_start__ = .; *(CodeQuickAccess) + /* The FlexSPI drivers must run from TCM while the flash is being + reconfigured, mirroring the Keil/IAR QuickAccess placement. */ + *fsl_flexspi.o(.text*) + *drv_flexspi_nor_flash.o(.text*) + *drv_flexspi.o(.text*) . = ALIGN(128); __ram_function_end__ = .; } > m_qacode diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_hyperram.scf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_hyperram.scf index 5f77343005db..e1596416ace0 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_hyperram.scf +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_hyperram.scf @@ -120,14 +120,14 @@ LR_m_text m_text_start m_text_size ER_m_QuickAccessCode m_qacode_start m_qacode_size { .ANY (CodeQuickAccess) + fsl_flexspi.o (+RO-CODE) + drv_flexspi_nor_flash.o (+RO-CODE) + drv_flexspi.o (+RO-CODE) } ER_m_QuickAccessData m_qadata_start m_qadata_size { .ANY (DataQuickAccess) - fsl_flexspi.o (+RO-CODE) - drv_flexspi_nor_flash.o (+RO-CODE) - drv_flexspi.o (+RO-CODE) } RW_m_data m_data_start m_data_size-stack_size diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_industry.icf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_industry.icf new file mode 100644 index 000000000000..7890d3950bd9 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_industry.icf @@ -0,0 +1,179 @@ +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm7 +** MIMXRT1189CVM8C_cm7 +** MIMXRT1189XVM8B_cm7 +** MIMXRT1189XVM8C_cm7 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** Industrial Ethernet configuration: +** - CM7 uses 512KB TCM (256KB ITCM + 256KB DTCM). +** - CM7 uses the whole OCRAM1 (heap + 256KB non-cacheable data). +** - CM7 uses 96KB OCRAM2 as extra RAM. +** - 32KB OCRAM2 is reserved as RPMsg shared memory. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Board memory map */ +define symbol m_itcm_start = 0x00000000; +define symbol m_itcm_size = 0x00040000; + +define symbol m_dtcm_start = 0x20000000; +define symbol m_dtcm_size = 0x00040000; + +define symbol m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */ +define symbol m_ocram1_size = 0x0007C000; + +define symbol m_ocram2_start = 0x20500000; +define symbol m_ocram2_size = 0x00040000; + +define symbol m_sdram_start = 0x80000000; +define symbol m_sdram_size = 0x01E00000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +define symbol m_hyperram_start = 0x04000000; +define symbol m_hyperram_size = 0x00600000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +define symbol m_flash_start = 0x28800000; +define symbol m_flash_size = 0x00800000; + +/* General definition */ +define symbol app_image_offset = 0x00000000; +define symbol vector_table_size = 0x00000400; +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x1000; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x10000; +} + +define symbol m_qacode_start = m_itcm_start + (isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0); +define symbol m_qacode_end = m_itcm_start + m_itcm_size - 1; +define symbol m_qadata_start = m_dtcm_start; +define symbol m_qadata_end = m_dtcm_start + m_dtcm_size - 1; +define symbol m_ram_vector_table_start = m_itcm_start; + +/* Target specific definition, code & data allocation */ +define symbol m_code_size = m_flash_size - app_image_offset; +define symbol m_data_size = m_dtcm_size; + +/* Industrial Ethernet configuration: + * CM7 uses the whole OCRAM1: 64KB heap (growable via __heap_size__ up to + * 240KB) and 256KB non-cacheable data. + * OCRAM2 layout (must match MIMXRT1189xxxxx_cm33_ram_industry.icf): + * [0x20500000, 0x2051FFFF] 128KB CM33 exclusive (heap + NCACHE) + * [0x20520000, 0x20537FFF] 96KB CM7 extra RAM (OCRAM2_DATA_region) + * [0x20538000, 0x2053FFFF] 32KB RPMsg shared memory + * NCACHE and shared memory sizes must be 2^N and the start addresses must be + * multiples of the size so that the MPU configuration in BOARD_ConfigMPU() + * stays valid. + */ +define symbol m_ncache_size = 0x40000; /* 256KB, must be 2^N */ +define symbol m_ncache_start = m_ocram1_start + m_ocram1_size - m_ncache_size; /* 0x204C0000 */ +define symbol m_ncache_end = m_ncache_start + m_ncache_size - 1; + +define symbol m_heap_start = m_ocram1_start; /* 0x20484000 */ +define symbol m_heap_end = m_ncache_start - 1; + +define symbol m_ocram2_data_start = 0x20520000; +define symbol m_ocram2_data_size = 0x18000; /* 96KB CM7 extra RAM */ +define symbol m_ocram2_data_end = m_ocram2_data_start + m_ocram2_data_size - 1; + +define symbol m_shmem_size = 0x8000; /* 32KB shared memory, must be 2^N */ +if (isdefinedsymbol(__use_shmem__)) { + define symbol m_rpmsg_sh_mem_start = m_ocram2_start + m_ocram2_size - m_shmem_size; /* 0x20538000 */ + define symbol m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; +} + +define symbol m_ram_vector_table_size = isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0; + +define symbol m_text_start = m_flash_start + app_image_offset; +define symbol m_text_end = m_text_start + m_code_size - 1; +define symbol m_interrupts_start = m_text_start; + +define symbol m_data_start = m_dtcm_start; +define symbol m_data_end = m_data_start + m_data_size - 1; + +/* Exported symbol definition */ +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_ram_vector_table_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = m_ram_vector_table_size; +define exported symbol __NCACHE_REGION_START = m_ncache_start; +define exported symbol __NCACHE_REGION_SIZE = m_ncache_end - m_ncache_start + 1; +/* 96KB OCRAM2 reserved for CM7 extra RAM (e.g. EtherCAT buffers), cacheable. + * The region is kept empty and can be initialized as a memheap at runtime + * using __OCRAM2_DATA_START and __OCRAM2_DATA_SIZE. */ +define exported symbol __OCRAM2_DATA_START = m_ocram2_data_start; +define exported symbol __OCRAM2_DATA_SIZE = m_ocram2_data_size; +if (isdefinedsymbol(__use_shmem__)) { + define exported symbol rpmsg_sh_mem_start = m_rpmsg_sh_mem_start; + define exported symbol rpmsg_sh_mem_end = m_rpmsg_sh_mem_end; + define exported symbol __RPMSG_SH_MEM_START = m_rpmsg_sh_mem_start; + define exported symbol __RPMSG_SH_MEM_SIZE = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1; +} + +/* Region definition */ +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; +define region HEAP_region = mem:[from m_heap_start to m_heap_end]; +define region QACODE_region = mem:[from m_qacode_start to m_qacode_end]; +define region QADATA_region = mem:[from m_qadata_start to m_qadata_end]; +define region OCRAM2_DATA_region = mem:[from m_ocram2_data_start to m_ocram2_data_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from m_rpmsg_sh_mem_start to m_rpmsg_sh_mem_end]; +} + +/* Block definition */ +define block RW { readwrite }; +define block ZI { zi }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; +define block QACCESS_CODE { section CodeQuickAccess }; +define block QACCESS_DATA { section DataQuickAccess }; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block OCRAM2_DATA with alignment = 8, size = m_ocram2_data_size { }; + +initialize by copy { readwrite, section .textrw, section DataQuickAccess, section CodeQuickAccess, + ro code object fsl_flexspi.o, ro code object drv_flexspi_nor_flash.o, ro code object drv_flexspi.o }; +do not initialize { section .noinit }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place in TEXT_region { readonly }; +place in QACODE_region { block QACCESS_CODE }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { block QACCESS_DATA }; +place in NCACHE_region { block NCACHE_VAR }; +place in OCRAM2_DATA_region { block OCRAM2_DATA }; +place in CSTACK_region { block CSTACK }; +if (isdefinedsymbol(__heap_noncacheable__)) { + place in NCACHE_region { last block HEAP }; +} else { + place in HEAP_region { last block HEAP }; +} +if (isdefinedsymbol(__use_shmem__)) { + place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_industry.ld b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_industry.ld new file mode 100644 index 000000000000..32547be72331 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_industry.ld @@ -0,0 +1,371 @@ +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm7 +** MIMXRT1189CVM8C_cm7 +** MIMXRT1189XVM8B_cm7 +** MIMXRT1189XVM8C_cm7 +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the GNU C Compiler +** Industrial Ethernet configuration: +** - CM7 uses 512KB TCM (256KB ITCM + 256KB DTCM). +** - CM7 uses the whole OCRAM1 (heap + 256KB non-cacheable data). +** - CM7 uses 96KB OCRAM2 as extra RAM. +** - 32KB OCRAM2 is reserved as RPMsg shared memory. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Board memory map */ +m_itcm_start = 0x00000000; +m_itcm_size = 0x00040000; +m_dtcm_start = 0x20000000; +m_dtcm_size = 0x00040000; +m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */ +m_ocram1_size = 0x0007C000; +m_ocram2_start = 0x20500000; +m_ocram2_size = 0x00040000; +m_sdram_start = 0x80000000; +m_sdram_size = 0x01E00000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +m_hyperram_start = 0x04000000; +m_hyperram_size = 0x00600000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +m_flash_start = 0x28800000; +m_flash_size = 0x00800000; + +/* General definition */ +app_image_offset = 0x00000000; +vector_table_size = 0x00000400; +m_qacode_start = m_itcm_start + (DEFINED(__ram_vector_table__) ? vector_table_size : 0); +m_qacode_end = m_itcm_start + m_dtcm_size - 1; +m_qadata_start = m_dtcm_start; +m_qadata_end = m_dtcm_start + m_dtcm_size - 1; +m_ram_vector_table_start = m_itcm_start; +m_stack_size = DEFINED(__stack_size__) ? __stack_size__ : 0x1000; +m_heap_size = DEFINED(__heap_size__) ? __heap_size__ : 0x10000; + +/* Target specific definition, code & data allocation */ +m_code_size = m_flash_size - app_image_offset - vector_table_size; +m_data_size = m_dtcm_size; + +/* Industrial Ethernet configuration: + * CM7 uses the whole OCRAM1: 64KB heap (growable via __heap_size__ up to + * 240KB) and 256KB non-cacheable data. + * OCRAM2 layout (must match MIMXRT1189xxxxx_cm33_ram_industry.ld): + * [0x20500000, 0x2051FFFF] 128KB CM33 exclusive (heap + NCACHE) + * [0x20520000, 0x20537FFF] 96KB CM7 extra RAM (m_ocram2) + * [0x20538000, 0x2053FFFF] 32KB RPMsg shared memory + * NCACHE and shared memory sizes must be 2^N and the start addresses must be + * multiples of the size so that the MPU configuration in BOARD_ConfigMPU() + * stays valid. + */ +m_ncache_size = 0x40000; /* 256KB, must be 2^N */ +m_ncache_start = m_ocram1_start + m_ocram1_size - m_ncache_size; /* 0x204C0000 */ +m_shmem_size = 0x8000; /* 32KB shared memory, must be 2^N */ + +m_ram_vector_table_size = DEFINED(__ram_vector_table__) ? vector_table_size : 0; + +m_interrupts_start = m_flash_start + app_image_offset; +m_interrupts_end = m_interrupts_start + vector_table_size - 1; + +m_text_start = m_interrupts_end + 1; +m_text_end = m_text_start + m_code_size - 1; + +m_data_start = m_dtcm_start; +m_data_end = m_data_start + m_data_size - 1; + +m_ncache_end = m_ncache_start + m_ncache_size - 1 - (DEFINED(__heap_noncacheable__) ? m_heap_size : 0); + +m_heap_start = DEFINED(__heap_noncacheable__) ? m_ncache_end + 1 : m_ocram1_start; /* 0x20484000 */ +m_heap_end = m_heap_start + m_heap_size - 1; + +/* 96KB OCRAM2 reserved for CM7 extra RAM (e.g. EtherCAT buffers), cacheable. + * The region is kept empty and can be initialized as a memheap at runtime + * using __OCRAM2_DATA_START and __OCRAM2_DATA_SIZE. */ +m_ocram2_data_start = 0x20520000; +m_ocram2_data_size = 0x18000; /* 96KB */ +m_ocram2_data_end = m_ocram2_data_start + m_ocram2_data_size - 1; + +m_rpmsg_sh_mem_start = m_ocram2_start + m_ocram2_size - m_shmem_size; /* 0x20538000 */ +m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; + +/* Exported symbol definition */ +__VECTOR_TABLE = m_interrupts_start; +__VECTOR_RAM = m_ram_vector_table_start; +__RAM_VECTOR_TABLE_SIZE_BYTES = m_ram_vector_table_size; + +__NCACHE_REGION_START = m_ncache_start; +__NCACHE_REGION_SIZE = m_ncache_size; +__RPMSG_SH_MEM_START = DEFINED(__use_shmem__)? m_rpmsg_sh_mem_start : 0; +__RPMSG_SH_MEM_SIZE = DEFINED(__use_shmem__)? m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1 : 0; +__OCRAM2_DATA_START = m_ocram2_data_start; +__OCRAM2_DATA_SIZE = m_ocram2_data_size; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts_ram (RX) : ORIGIN = m_ram_vector_table_start, LENGTH = __RAM_VECTOR_TABLE_SIZE_BYTES + m_interrupts (RX) : ORIGIN = m_interrupts_start, LENGTH = m_interrupts_end - m_interrupts_start + 1 + m_text (RX) : ORIGIN = m_text_start, LENGTH = m_text_end - m_text_start + 1 + m_data (RW) : ORIGIN = m_data_start, LENGTH = m_data_end - m_data_start + 1 + m_ncache (RW) : ORIGIN = m_ncache_start, LENGTH = m_ncache_end - m_ncache_start + 1 + m_heap (RW) : ORIGIN = m_heap_start, LENGTH = m_heap_end - m_heap_start + 1 + m_qacode (RX) : ORIGIN = m_qacode_start, LENGTH = m_qacode_end - m_qacode_start + 1 + m_qadata (RW) : ORIGIN = m_qadata_start, LENGTH = m_qadata_end - m_qadata_start + 1 + m_ocram2 (RW) : ORIGIN = m_ocram2_data_start, LENGTH = m_ocram2_data_size + m_rpmsg (RW) : ORIGIN = m_rpmsg_sh_mem_start, LENGTH = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first */ + .interrupts : + { + . = ALIGN(4); + __Vectors = .; + KEEP(*(.isr_vector)) /* Vector table and startup code */ + . = ALIGN(4); + } > m_interrupts + + .interrupts_ram : + { + . = ALIGN(4); + . += __RAM_VECTOR_TABLE_SIZE_BYTES; + . = ALIGN(4); + } > m_interrupts_ram + + /* The program code */ + .text : + { + . = ALIGN(4); + *(EXCLUDE_FILE(*fsl_flexspi.o *drv_flexspi_nor_flash.o *drv_flexspi.o) .text) + *(EXCLUDE_FILE(*fsl_flexspi.o *drv_flexspi_nor_flash.o *drv_flexspi.o) .text*) + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + + /* RT-Thread FinSH symbol table */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + /* RT-Thread init table */ + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* RT-Thread init functions */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + + __data_flash_start = .; /* Symbol is used by startup for data initialization */ + .data : AT(__data_flash_start) + { + . = ALIGN(4); + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(DataQuickAccess) /* quick access data section */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __ram_function_flash_start = __data_flash_start + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM code initialization */ + .ram_function : AT(__ram_function_flash_start) + { + . = ALIGN(32); + __ram_function_start__ = .; + *(CodeQuickAccess) + /* The FlexSPI drivers must run from TCM while the flash is being + reconfigured, mirroring the Keil/IAR QuickAccess placement. */ + *fsl_flexspi.o(.text*) + *drv_flexspi_nor_flash.o(.text*) + *drv_flexspi.o(.text*) + . = ALIGN(128); + __ram_function_end__ = .; + } > m_qacode + + __noncache_data_flash_start = __ram_function_flash_start + (__ram_function_end__ - __ram_function_start__); + .ncache.init : AT(__noncache_data_flash_start) + { + . = ALIGN(4); + __noncache_data_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncache_data_end__ = .; /* create a global symbol at ncache data end */ + } > m_ncache + + .ncache : + { + . = ALIGN(4); + __noncache_bss_start__ = .; /* define a global symbol at ncache bss start */ + *(NonCacheable) + . = ALIGN(4); + __noncache_bss_end__ = .; /* define a global symbol at ncache bss end */ + } > m_ncache + + __qadata_flash_start = __noncache_data_flash_start + (__noncache_data_end__ - __noncache_data_start__); + .qadata : AT(__qadata_flash_start) + { + . = ALIGN(4); + __qadata_start__ = .; + . = ALIGN(4); + __qadata_end__ = .; + } > m_qadata + + text_data_end = __qadata_flash_start + (__qadata_end__ - __qadata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(text_data_end < text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > m_data + + /* 96KB OCRAM2 reserved for CM7 extra RAM (e.g. EtherCAT buffers). + * Kept empty; initialize as a memheap at runtime. */ + .ocram2 : + { + . = ALIGN(4); + __ocram2_data_start = .; + . += m_ocram2_data_size; + __ocram2_data_end = .; + . = ALIGN(4); + } > m_ocram2 + + .rpmsg : + { + *(.noinit.$rpmsg_sh_mem) + } > m_rpmsg + + .heap : + { + . = ALIGN(8); + __HeapBase = .; + end = .; + . += m_heap_size; + __HeapLimit = .; /* Add for _sbrk */ + } > m_heap + + .stack : + { + . = ALIGN(8); + __StackStart = .; + . += m_stack_size; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - m_stack_size; + PROVIDE(__stack = __StackTop); + PROVIDE (__stack_size = m_stack_size); + ASSERT(__StackLimit >= __StackStart, "region m_data overflowed with stack and heap") + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_industry.scf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_industry.scf new file mode 100644 index 000000000000..606d6afa75df --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_flexspi_nor_industry.scf @@ -0,0 +1,199 @@ +#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm7 +** MIMXRT1189CVM8C_cm7 +** MIMXRT1189XVM8B_cm7 +** MIMXRT1189XVM8C_cm7 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** Industrial Ethernet configuration: +** - CM7 uses 512KB TCM (256KB ITCM + 256KB DTCM). +** - CM7 uses the whole OCRAM1 (heap + 256KB non-cacheable data). +** - CM7 uses 96KB OCRAM2 as extra RAM. +** - 32KB OCRAM2 is reserved as RPMsg shared memory. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* Board memory map */ + +#define m_itcm_start 0x00000000 +#define m_itcm_size 0x00040000 + +#define m_dtcm_start 0x20000000 +#define m_dtcm_size 0x00040000 + +#define m_ocram1_start 0x20484000 /* OCRAM1 first 16K access is blocked by TRDC */ +#define m_ocram1_size 0x0007C000 + +#define m_ocram2_start 0x20500000 +#define m_ocram2_size 0x00040000 + +#define m_sdram_start 0x80000000 +#define m_sdram_size 0x01E00000 /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +#define m_hyperram_start 0x04000000 +#define m_hyperram_size 0x00600000 /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +#define m_flash_start 0x28800000 +#define m_flash_size 0x00800000 + +/* General definition */ +#define app_image_offset 0x00000000 +#define vector_table_size 0x400 +#define m_ram_vector_table_start m_itcm_start + +#if defined(__stack_size__) + #define stack_size __stack_size__ +#else + #define stack_size 0x01000 +#endif + +#if defined(__heap_size__) + #define heap_size __heap_size__ +#else + #define heap_size 0x10000 +#endif + +/* Target specific definition, code & data allocation */ +#if defined(__ram_vector_table__) +#define m_ram_vector_table_size vector_table_size +#else +#define m_ram_vector_table_size 0 +#endif + +#define m_qacode_start m_itcm_start + m_ram_vector_table_size +#define m_qadata_start m_dtcm_start +#define m_qacode_size m_itcm_size - (m_qacode_start - m_itcm_start) +#define m_qadata_size 0 + +#define m_text_size m_flash_size - app_image_offset +#define m_data_size m_dtcm_size + +/* Industrial Ethernet configuration: + * CM7 uses the whole OCRAM1: 64KB heap (growable via __heap_size__ up to + * 240KB) and 256KB non-cacheable data. + * OCRAM2 layout (must match MIMXRT1189xxxxx_cm33_ram_industry.scf): + * [0x20500000, 0x2051FFFF] 128KB CM33 exclusive (heap + NCACHE) + * [0x20520000, 0x20537FFF] 96KB CM7 extra RAM (RW_m_ocram2) + * [0x20538000, 0x2053FFFF] 32KB RPMsg shared memory + * NCACHE and shared memory sizes must be 2^N and the start addresses must be + * multiples of the size so that the MPU configuration in BOARD_ConfigMPU() + * stays valid. + */ +#define m_ncache_size 0x40000 /* 256KB, must be 2^N */ +#define m_ncache_start m_ocram1_start + m_ocram1_size - m_ncache_size /* 0x204C0000 */ +#define m_heap_start m_ocram1_start /* 0x20484000 */ + +#define m_ocram2_data_start 0x20520000 +#define m_ocram2_data_size 0x18000 /* 96KB CM7 extra RAM */ + +#define m_shmem_size 0x8000 /* 32KB shared memory, must be 2^N */ +#define m_shmem_start m_ocram2_start + m_ocram2_size - m_shmem_size /* 0x20538000 */ + +#define m_text_start m_flash_start + app_image_offset +#define m_interrupts_start m_text_start +#define m_data_start m_dtcm_start + +; load region +LR_m_text m_text_start m_text_size +{ + ; load address = execution address + VECTOR_ROM m_interrupts_start FIXED vector_table_size + { + * (.isr_vector,+FIRST) + } + + VECTOR_RAM m_ram_vector_table_start EMPTY m_ram_vector_table_size + { + } + + ; load address = execution address + ER_m_text m_text_start + vector_table_size FIXED m_text_size - vector_table_size + { + * (InRoot$$Sections) + .ANY (+RO) + } + + ER_m_QuickAccessCode m_qacode_start m_qacode_size + { + .ANY (CodeQuickAccess) + fsl_flexspi.o (+RO-CODE) + drv_flexspi_nor_flash.o (+RO-CODE) + drv_flexspi.o (+RO-CODE) + } + + ER_m_QuickAccessData m_qadata_start EMPTY m_qadata_size + { + } + + RW_m_data m_data_start m_data_size-stack_size + { + .ANY (+RW +ZI) + .ANY (DataQuickAccess) + } + + ; ncache data + RW_m_ncache m_ncache_start m_ncache_size + { + .ANY (NonCacheable.init) + .ANY (.bss.NonCacheable) + } + +#if defined(__heap_noncacheable__) + ; Heap region growing up + ARM_LIB_HEAP +0 ALIGN 0x100 EMPTY heap_size + { + } +#endif + + ; Empty region added for MPU configuration + RW_m_ncache_aux m_ncache_start + m_ncache_size EMPTY 0 + { + } + + ; 96KB OCRAM2 reserved for CM7 extra RAM (e.g. EtherCAT buffers). + ; The region is cacheable and can be initialized as a memheap at runtime + ; using Image$$RW_m_ocram2$$Base and Image$$RW_m_ocram2$$Limit. + RW_m_ocram2 m_ocram2_data_start EMPTY m_ocram2_data_size + { + } + +#if defined(__use_shmem__) + ; shared memory data + RPMSG_SH_MEM m_shmem_start m_shmem_size + { + .ANY (rpmsg_sh_mem_section) + } + + ; Empty region added for MPU configuration + RPMSG_SH_MEM_aux m_shmem_start + m_shmem_size EMPTY 0 + { + } +#endif + +#if !defined(__heap_noncacheable__) + ; Heap region growing up + ARM_LIB_HEAP m_heap_start EMPTY heap_size + { + } +#endif + + ; Stack region growing down + ARM_LIB_STACK m_data_start+m_data_size EMPTY -stack_size + { + } +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_hyperram.icf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_hyperram.icf index f5d3f6296550..639055565b54 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_hyperram.icf +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_hyperram.icf @@ -1,156 +1,156 @@ -/* -** ################################################################### -** Processors: MIMXRT1189CVM8B_cm7 -** MIMXRT1189CVM8C_cm7 -** MIMXRT1189XVM8B_cm7 -** MIMXRT1189XVM8C_cm7 -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: IMXRT1180RM, Rev 5, 01/2024 -** Version: rev. 2.0, 2024-01-18 -** Build: b250310 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2025 NXP -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -/* Board memory map */ -define symbol m_itcm_start = 0x00000000; -define symbol m_itcm_size = 0x00040000; - -define symbol m_dtcm_start = 0x20000000; -define symbol m_dtcm_size = 0x00040000; - -define symbol m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */ -define symbol m_ocram1_size = 0x0007C000; - -define symbol m_ocram2_start = 0x20500000; -define symbol m_ocram2_size = 0x00040000; - -define symbol m_sdram_start = 0x80000000; -define symbol m_sdram_size = 0x01E00000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ -define symbol m_hyperram_start = 0x04000000; -define symbol m_hyperram_size = 0x00600000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ -define symbol m_flash_start = 0x28000000; -define symbol m_flash_size = 0x01000000; - -/* General definition */ -define symbol app_image_offset = 0x0000B000; -define symbol vector_table_size = 0x00000400; -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x8000; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x4000; -} - -define symbol m_qacode_start = m_itcm_start + (isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0); -define symbol m_qacode_end = m_itcm_start + m_itcm_size - 1; -define symbol m_qadata_start = m_dtcm_start; -define symbol m_qadata_end = m_dtcm_start + m_dtcm_size - 1; -define symbol m_ram_vector_table_start = m_itcm_start; - -/* Target specific definition, code & data allocation */ -define symbol m_code_size = m_itcm_size; -define symbol m_data_size = 0x00600000; -define symbol m_ncache_size = isdefinedsymbol(__multicore__) ? 0x20000 : 0x40000; /* m_ncache_size must be 2^N */ -define symbol m_shmem_size = m_ocram2_size; /* m_shmem_size must be 2^N */ - -define symbol m_ocram1_size_for_cm7 = isdefinedsymbol(__multicore__) ? 0x40000 : m_ocram1_size; - -define symbol m_ram_vector_table_size = isdefinedsymbol(__ram_vector_table__) ? 0 : 0; - -define symbol m_text_start = m_itcm_start; -define symbol m_text_end = m_text_start + m_code_size - 1; -define symbol m_interrupts_start = m_text_start; - -define symbol m_data_start = m_hyperram_start; -define symbol m_data_end = m_data_start + m_data_size - 1; - -define symbol m_ncache_start = m_ocram1_start + m_ocram1_size - m_ncache_size; /* (m_ncache_start % m_ncache_size) must be 0 */ -define symbol m_ncache_end = m_ncache_start + m_ncache_size - 1; - -define symbol m_heap_start = m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7; -define symbol m_heap_end = m_ncache_start - 1; - -if (isdefinedsymbol(__use_shmem__)) { - define symbol m_rpmsg_sh_mem_start = m_ocram2_start; /* (m_rpmsg_sh_mem_start % m_shmem_size) must be 0 */ - define symbol m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; -} - -/* Exported symbol definition */ -define exported symbol __VECTOR_TABLE = m_interrupts_start; -define exported symbol __VECTOR_RAM = m_ram_vector_table_start; -define exported symbol __RAM_VECTOR_TABLE_SIZE = m_ram_vector_table_size; -define exported symbol __NCACHE_REGION_START = m_ncache_start; -define exported symbol __NCACHE_REGION_SIZE = m_ncache_end - m_ncache_start + 1; -if (isdefinedsymbol(__use_shmem__)) { - define exported symbol rpmsg_sh_mem_start = m_rpmsg_sh_mem_start; - define exported symbol rpmsg_sh_mem_end = m_rpmsg_sh_mem_end; - define exported symbol __RPMSG_SH_MEM_START = m_rpmsg_sh_mem_start; - define exported symbol __RPMSG_SH_MEM_SIZE = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1; -} - -/* Region definition */ -define memory mem with size = 4G; -define region TEXT_region = mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; -define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; -define region HEAP_region = mem:[from m_heap_start to m_heap_end]; -define region QACODE_region = mem:[from m_qacode_start to m_qacode_end]; -define region QADATA_region = mem:[from m_qadata_start to m_qadata_end]; -if (isdefinedsymbol(__use_shmem__)) { - define region rpmsg_sh_mem_region = mem:[from m_rpmsg_sh_mem_start to m_rpmsg_sh_mem_end]; -} - -/* Block definition */ -define block RW { readwrite }; -define block ZI { zi }; -define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; -define block QACCESS_CODE { section CodeQuickAccess }; -define block QACCESS_DATA { section DataQuickAccess }; -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; - -/* cache line size = 32 bytes */ -define block CACHE_LINE_DATA_ZI with alignment = 32, end alignment = 32 { section CacheLineData }; -define block CACHE_LINE_DATA_RW with alignment = 32, end alignment = 32 { section CacheLineData.init }; - -initialize by copy { readwrite, section .textrw, section DataQuickAccess }; -do not initialize { section .noinit }; -if (isdefinedsymbol(__use_shmem__)) { - do not initialize { section rpmsg_sh_mem_section }; -} - -place at address mem: m_interrupts_start { readonly section .intvec }; - -place in TEXT_region { readonly }; -place in TEXT_region { block QACCESS_CODE }; -place in DATA_region { block RW, block CACHE_LINE_DATA_RW }; -place in DATA_region { block ZI, block CACHE_LINE_DATA_ZI }; -place in QADATA_region { block QACCESS_DATA }; -place in NCACHE_region { block NCACHE_VAR }; -place in CSTACK_region { block CSTACK }; -if (isdefinedsymbol(__heap_noncacheable__)) { - place in NCACHE_region { last block HEAP }; -} else { - place in HEAP_region { last block HEAP }; -} -if (isdefinedsymbol(__use_shmem__)) { - place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; -} +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm7 +** MIMXRT1189CVM8C_cm7 +** MIMXRT1189XVM8B_cm7 +** MIMXRT1189XVM8C_cm7 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Board memory map */ +define symbol m_itcm_start = 0x00000000; +define symbol m_itcm_size = 0x00040000; + +define symbol m_dtcm_start = 0x20000000; +define symbol m_dtcm_size = 0x00040000; + +define symbol m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */ +define symbol m_ocram1_size = 0x0007C000; + +define symbol m_ocram2_start = 0x20500000; +define symbol m_ocram2_size = 0x00040000; + +define symbol m_sdram_start = 0x80000000; +define symbol m_sdram_size = 0x01E00000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +define symbol m_hyperram_start = 0x04000000; +define symbol m_hyperram_size = 0x00600000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +define symbol m_flash_start = 0x28000000; +define symbol m_flash_size = 0x01000000; + +/* General definition */ +define symbol app_image_offset = 0x0000B000; +define symbol vector_table_size = 0x00000400; +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x1000; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x8000; +} + +define symbol m_qacode_start = m_itcm_start + (isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0); +define symbol m_qacode_end = m_itcm_start + m_itcm_size - 1; +define symbol m_qadata_start = m_dtcm_start; +define symbol m_qadata_end = m_dtcm_start + m_dtcm_size - 1; +define symbol m_ram_vector_table_start = m_itcm_start; + +/* Target specific definition, code & data allocation */ +define symbol m_code_size = m_itcm_size; +define symbol m_data_size = 0x00600000; +define symbol m_ncache_size = isdefinedsymbol(__multicore__) ? 0x20000 : 0x40000; /* m_ncache_size must be 2^N */ +define symbol m_shmem_size = m_ocram2_size; /* m_shmem_size must be 2^N */ + +define symbol m_ocram1_size_for_cm7 = isdefinedsymbol(__multicore__) ? 0x40000 : m_ocram1_size; + +define symbol m_ram_vector_table_size = isdefinedsymbol(__ram_vector_table__) ? 0 : 0; + +define symbol m_text_start = m_itcm_start; +define symbol m_text_end = m_text_start + m_code_size - 1; +define symbol m_interrupts_start = m_text_start; + +define symbol m_data_start = m_hyperram_start; +define symbol m_data_end = m_data_start + m_data_size - 1; + +define symbol m_ncache_start = m_ocram1_start + m_ocram1_size - m_ncache_size; /* (m_ncache_start % m_ncache_size) must be 0 */ +define symbol m_ncache_end = m_ncache_start + m_ncache_size - 1; + +define symbol m_heap_start = m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7; +define symbol m_heap_end = m_ncache_start - 1; + +if (isdefinedsymbol(__use_shmem__)) { + define symbol m_rpmsg_sh_mem_start = m_ocram2_start; /* (m_rpmsg_sh_mem_start % m_shmem_size) must be 0 */ + define symbol m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; +} + +/* Exported symbol definition */ +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_ram_vector_table_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = m_ram_vector_table_size; +define exported symbol __NCACHE_REGION_START = m_ncache_start; +define exported symbol __NCACHE_REGION_SIZE = m_ncache_end - m_ncache_start + 1; +if (isdefinedsymbol(__use_shmem__)) { + define exported symbol rpmsg_sh_mem_start = m_rpmsg_sh_mem_start; + define exported symbol rpmsg_sh_mem_end = m_rpmsg_sh_mem_end; + define exported symbol __RPMSG_SH_MEM_START = m_rpmsg_sh_mem_start; + define exported symbol __RPMSG_SH_MEM_SIZE = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1; +} + +/* Region definition */ +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; +define region HEAP_region = mem:[from m_heap_start to m_heap_end]; +define region QACODE_region = mem:[from m_qacode_start to m_qacode_end]; +define region QADATA_region = mem:[from m_qadata_start to m_qadata_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from m_rpmsg_sh_mem_start to m_rpmsg_sh_mem_end]; +} + +/* Block definition */ +define block RW { readwrite }; +define block ZI { zi }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; +define block QACCESS_CODE { section CodeQuickAccess }; +define block QACCESS_DATA { section DataQuickAccess }; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; + +/* cache line size = 32 bytes */ +define block CACHE_LINE_DATA_ZI with alignment = 32, end alignment = 32 { section CacheLineData }; +define block CACHE_LINE_DATA_RW with alignment = 32, end alignment = 32 { section CacheLineData.init }; + +initialize by copy { readwrite, section .textrw, section DataQuickAccess }; +do not initialize { section .noinit }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place in TEXT_region { readonly }; +place in TEXT_region { block QACCESS_CODE }; +place in DATA_region { block RW, block CACHE_LINE_DATA_RW }; +place in DATA_region { block ZI, block CACHE_LINE_DATA_ZI }; +place in QADATA_region { block QACCESS_DATA }; +place in NCACHE_region { block NCACHE_VAR }; +place in CSTACK_region { block CSTACK }; +if (isdefinedsymbol(__heap_noncacheable__)) { + place in NCACHE_region { last block HEAP }; +} else { + place in HEAP_region { last block HEAP }; +} +if (isdefinedsymbol(__use_shmem__)) { + place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_ram.icf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_ram.icf index 232bebba5ef0..b272ef7be1df 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_ram.icf +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_ram.icf @@ -1,152 +1,152 @@ -/* -** ################################################################### -** Processors: MIMXRT1189CVM8B_cm7 -** MIMXRT1189CVM8C_cm7 -** MIMXRT1189XVM8B_cm7 -** MIMXRT1189XVM8C_cm7 -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: IMXRT1180RM, Rev 5, 01/2024 -** Version: rev. 2.0, 2024-01-18 -** Build: b250310 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2025 NXP -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -/* Board memory map */ -define symbol m_itcm_start = 0x00000000; -define symbol m_itcm_size = 0x00040000; - -define symbol m_dtcm_start = 0x20000000; -define symbol m_dtcm_size = 0x00040000; - -define symbol m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */ -define symbol m_ocram1_size = 0x0007C000; - -define symbol m_ocram2_start = 0x20500000; -define symbol m_ocram2_size = 0x00040000; - -define symbol m_sdram_start = 0x80000000; -define symbol m_sdram_size = 0x01E00000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ -define symbol m_hyperram_start = 0x04000000; -define symbol m_hyperram_size = 0x00600000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ -define symbol m_flash_start = 0x28000000; -define symbol m_flash_size = 0x01000000; - -/* General definition */ -define symbol app_image_offset = 0x0000B000; -define symbol vector_table_size = 0x00000400; -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x1000; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x8000; -} - -define symbol m_qacode_start = m_itcm_start + (isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0); -define symbol m_qacode_end = m_itcm_start + m_itcm_size - 1; -define symbol m_qadata_start = m_dtcm_start; -define symbol m_qadata_end = m_dtcm_start + m_dtcm_size - 1; -define symbol m_ram_vector_table_start = m_itcm_start; - -/* Target specific definition, code & data allocation */ -define symbol m_code_size = m_itcm_size; -define symbol m_data_size = m_dtcm_size; -define symbol m_ncache_size = isdefinedsymbol(__multicore__) ? 0x20000 : 0x40000; /* m_ncache_size must be 2^N */ -define symbol m_shmem_size = m_ocram2_size; /* m_shmem_size must be 2^N */ - -define symbol m_ocram1_size_for_cm7 = isdefinedsymbol(__multicore__) ? 0x40000 : m_ocram1_size; - -define symbol m_ram_vector_table_size = isdefinedsymbol(__ram_vector_table__) ? 0 : 0; - -define symbol m_text_start = m_itcm_start; -define symbol m_text_end = m_text_start + m_code_size - 1; -define symbol m_interrupts_start = m_text_start; - -define symbol m_data_start = m_dtcm_start; -define symbol m_data_end = m_data_start + m_data_size - 1; - -define symbol m_ncache_start = m_ocram1_start + m_ocram1_size - m_ncache_size; /* (m_ncache_start % m_ncache_size) must be 0 */ -define symbol m_ncache_end = m_ncache_start + m_ncache_size - 1; - -define symbol m_heap_start = m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7; -define symbol m_heap_end = m_ncache_start - 1; - -if (isdefinedsymbol(__use_shmem__)) { - define symbol m_rpmsg_sh_mem_start = m_ocram2_start; /* (m_rpmsg_sh_mem_start % m_shmem_size) must be 0 */ - define symbol m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; -} - -/* Exported symbol definition */ -define exported symbol __VECTOR_TABLE = m_interrupts_start; -define exported symbol __VECTOR_RAM = m_ram_vector_table_start; -define exported symbol __RAM_VECTOR_TABLE_SIZE = m_ram_vector_table_size; -define exported symbol __NCACHE_REGION_START = m_ncache_start; -define exported symbol __NCACHE_REGION_SIZE = m_ncache_end - m_ncache_start + 1; -if (isdefinedsymbol(__use_shmem__)) { - define exported symbol rpmsg_sh_mem_start = m_rpmsg_sh_mem_start; - define exported symbol rpmsg_sh_mem_end = m_rpmsg_sh_mem_end; - define exported symbol __RPMSG_SH_MEM_START = m_rpmsg_sh_mem_start; - define exported symbol __RPMSG_SH_MEM_SIZE = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1; -} - -/* Region definition */ -define memory mem with size = 4G; -define region TEXT_region = mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; -define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; -define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; -define region HEAP_region = mem:[from m_heap_start to m_heap_end]; -define region QACODE_region = mem:[from m_qacode_start to m_qacode_end]; -define region QADATA_region = mem:[from m_qadata_start to m_qadata_end]; -if (isdefinedsymbol(__use_shmem__)) { - define region rpmsg_sh_mem_region = mem:[from m_rpmsg_sh_mem_start to m_rpmsg_sh_mem_end]; -} - -/* Block definition */ -define block RW { readwrite }; -define block ZI { zi }; -define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; -define block QACCESS_CODE { section CodeQuickAccess }; -define block QACCESS_DATA { section DataQuickAccess }; -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; - -initialize by copy { readwrite, section .textrw, section DataQuickAccess }; -do not initialize { section .noinit }; -if (isdefinedsymbol(__use_shmem__)) { - do not initialize { section rpmsg_sh_mem_section }; -} - -place at address mem: m_interrupts_start { readonly section .intvec }; - -place in TEXT_region { readonly }; -place in TEXT_region { block QACCESS_CODE }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { block QACCESS_DATA }; -place in NCACHE_region { block NCACHE_VAR }; -place in CSTACK_region { block CSTACK }; -if (isdefinedsymbol(__heap_noncacheable__)) { - place in NCACHE_region { last block HEAP }; -} else { - place in HEAP_region { last block HEAP }; -} -if (isdefinedsymbol(__use_shmem__)) { - place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; -} +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm7 +** MIMXRT1189CVM8C_cm7 +** MIMXRT1189XVM8B_cm7 +** MIMXRT1189XVM8C_cm7 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Board memory map */ +define symbol m_itcm_start = 0x00000000; +define symbol m_itcm_size = 0x00040000; + +define symbol m_dtcm_start = 0x20000000; +define symbol m_dtcm_size = 0x00040000; + +define symbol m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */ +define symbol m_ocram1_size = 0x0007C000; + +define symbol m_ocram2_start = 0x20500000; +define symbol m_ocram2_size = 0x00040000; + +define symbol m_sdram_start = 0x80000000; +define symbol m_sdram_size = 0x01E00000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +define symbol m_hyperram_start = 0x04000000; +define symbol m_hyperram_size = 0x00600000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +define symbol m_flash_start = 0x28000000; +define symbol m_flash_size = 0x01000000; + +/* General definition */ +define symbol app_image_offset = 0x0000B000; +define symbol vector_table_size = 0x00000400; +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x1000; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x8000; +} + +define symbol m_qacode_start = m_itcm_start + (isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0); +define symbol m_qacode_end = m_itcm_start + m_itcm_size - 1; +define symbol m_qadata_start = m_dtcm_start; +define symbol m_qadata_end = m_dtcm_start + m_dtcm_size - 1; +define symbol m_ram_vector_table_start = m_itcm_start; + +/* Target specific definition, code & data allocation */ +define symbol m_code_size = m_itcm_size; +define symbol m_data_size = m_dtcm_size; +define symbol m_ncache_size = isdefinedsymbol(__multicore__) ? 0x20000 : 0x40000; /* m_ncache_size must be 2^N */ +define symbol m_shmem_size = m_ocram2_size; /* m_shmem_size must be 2^N */ + +define symbol m_ocram1_size_for_cm7 = isdefinedsymbol(__multicore__) ? 0x40000 : m_ocram1_size; + +define symbol m_ram_vector_table_size = isdefinedsymbol(__ram_vector_table__) ? 0 : 0; + +define symbol m_text_start = m_itcm_start; +define symbol m_text_end = m_text_start + m_code_size - 1; +define symbol m_interrupts_start = m_text_start; + +define symbol m_data_start = m_dtcm_start; +define symbol m_data_end = m_data_start + m_data_size - 1; + +define symbol m_ncache_start = m_ocram1_start + m_ocram1_size - m_ncache_size; /* (m_ncache_start % m_ncache_size) must be 0 */ +define symbol m_ncache_end = m_ncache_start + m_ncache_size - 1; + +define symbol m_heap_start = m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7; +define symbol m_heap_end = m_ncache_start - 1; + +if (isdefinedsymbol(__use_shmem__)) { + define symbol m_rpmsg_sh_mem_start = m_ocram2_start; /* (m_rpmsg_sh_mem_start % m_shmem_size) must be 0 */ + define symbol m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; +} + +/* Exported symbol definition */ +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_ram_vector_table_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = m_ram_vector_table_size; +define exported symbol __NCACHE_REGION_START = m_ncache_start; +define exported symbol __NCACHE_REGION_SIZE = m_ncache_end - m_ncache_start + 1; +if (isdefinedsymbol(__use_shmem__)) { + define exported symbol rpmsg_sh_mem_start = m_rpmsg_sh_mem_start; + define exported symbol rpmsg_sh_mem_end = m_rpmsg_sh_mem_end; + define exported symbol __RPMSG_SH_MEM_START = m_rpmsg_sh_mem_start; + define exported symbol __RPMSG_SH_MEM_SIZE = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1; +} + +/* Region definition */ +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; +define region HEAP_region = mem:[from m_heap_start to m_heap_end]; +define region QACODE_region = mem:[from m_qacode_start to m_qacode_end]; +define region QADATA_region = mem:[from m_qadata_start to m_qadata_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from m_rpmsg_sh_mem_start to m_rpmsg_sh_mem_end]; +} + +/* Block definition */ +define block RW { readwrite }; +define block ZI { zi }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; +define block QACCESS_CODE { section CodeQuickAccess }; +define block QACCESS_DATA { section DataQuickAccess }; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; + +initialize by copy { readwrite, section .textrw, section DataQuickAccess }; +do not initialize { section .noinit }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place in TEXT_region { readonly }; +place in TEXT_region { block QACCESS_CODE }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { block QACCESS_DATA }; +place in NCACHE_region { block NCACHE_VAR }; +place in CSTACK_region { block CSTACK }; +if (isdefinedsymbol(__heap_noncacheable__)) { + place in NCACHE_region { last block HEAP }; +} else { + place in HEAP_region { last block HEAP }; +} +if (isdefinedsymbol(__use_shmem__)) { + place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_ram_industry.icf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_ram_industry.icf new file mode 100644 index 000000000000..f4270e45a9fd --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_ram_industry.icf @@ -0,0 +1,115 @@ +define symbol m_itcm_start = 0x00000000; +define symbol m_itcm_size = 0x00040000; +define symbol m_dtcm_start = 0x20000000; +define symbol m_dtcm_size = 0x00040000; +define symbol m_ocram1_start = 0x20484000; +define symbol m_ocram1_size = 0x0007C000; +define symbol m_ocram2_start = 0x20500000; +define symbol m_ocram2_size = 0x00040000; +define symbol m_sdram_start = 0x80000000; +define symbol m_sdram_size = 0x01E00000; +define symbol m_hyperram_start = 0x04000000; +define symbol m_hyperram_size = 0x00600000; +define symbol m_flash_start = 0x28000000; +define symbol m_flash_size = 0x01000000; + +define symbol app_image_offset = 0x0000B000; +define symbol vector_table_size = 0x00000400; +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x1000; +} +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x10000; +} + +define symbol m_qacode_start = m_itcm_start + (isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0); +define symbol m_qacode_end = m_itcm_start + m_itcm_size - 1; +define symbol m_qadata_start = m_dtcm_start; +define symbol m_qadata_end = m_dtcm_start + m_dtcm_size - 1; +define symbol m_ram_vector_table_start = m_itcm_start; +define symbol m_ram_vector_table_size = 0; +define symbol m_code_size = m_itcm_size; +define symbol m_data_size = m_dtcm_size; +define symbol m_text_start = m_itcm_start; +define symbol m_text_end = m_text_start + m_code_size - 1; +define symbol m_interrupts_start = m_text_start; +define symbol m_data_start = m_dtcm_start; +define symbol m_data_end = m_data_start + m_data_size - 1; + +define symbol m_ncache_size = 0x40000; +define symbol m_ncache_start = m_ocram1_start + m_ocram1_size - m_ncache_size; +define symbol m_ncache_end = m_ncache_start + m_ncache_size - 1; +define symbol m_heap_start = m_ocram1_start; +define symbol m_heap_end = m_ncache_start - 1; +define symbol m_ocram2_data_start = 0x20520000; +define symbol m_ocram2_data_size = 0x18000; +define symbol m_ocram2_data_end = m_ocram2_data_start + m_ocram2_data_size - 1; +define symbol m_shmem_size = 0x8000; +if (isdefinedsymbol(__use_shmem__)) { + define symbol m_rpmsg_sh_mem_start = m_ocram2_start + m_ocram2_size - m_shmem_size; + define symbol m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_ram_vector_table_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = m_ram_vector_table_size; +define exported symbol __NCACHE_REGION_START = m_ncache_start; +define exported symbol __NCACHE_REGION_SIZE = m_ncache_size; +define exported symbol __OCRAM2_DATA_START = m_ocram2_data_start; +define exported symbol __OCRAM2_DATA_SIZE = m_ocram2_data_size; +if (isdefinedsymbol(__use_shmem__)) { + define exported symbol rpmsg_sh_mem_start = m_rpmsg_sh_mem_start; + define exported symbol rpmsg_sh_mem_end = m_rpmsg_sh_mem_end; + define exported symbol __RPMSG_SH_MEM_START = m_rpmsg_sh_mem_start; + define exported symbol __RPMSG_SH_MEM_SIZE = m_shmem_size; +} + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; +define region HEAP_region = mem:[from m_heap_start to m_heap_end]; +define region QACODE_region = mem:[from m_qacode_start to m_qacode_end]; +define region QADATA_region = mem:[from m_qadata_start to m_qadata_end]; +define region OCRAM2_DATA_region = mem:[from m_ocram2_data_start to m_ocram2_data_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from m_rpmsg_sh_mem_start to m_rpmsg_sh_mem_end]; +} + +define block RW { readwrite }; +define block ZI { zi }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; +define block QACCESS_CODE { section CodeQuickAccess }; +define block QACCESS_DATA { section DataQuickAccess }; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block OCRAM2_DATA with alignment = 8, size = m_ocram2_data_size { }; + +initialize by copy { readwrite, section .textrw, section DataQuickAccess }; +do not initialize { section .noinit }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in TEXT_region { readonly }; +place in TEXT_region { block QACCESS_CODE }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { block QACCESS_DATA }; +place in NCACHE_region { block NCACHE_VAR }; +place in OCRAM2_DATA_region { block OCRAM2_DATA }; +place in CSTACK_region { block CSTACK }; +if (isdefinedsymbol(__heap_noncacheable__)) { + place in NCACHE_region { last block HEAP }; +} else { + place in HEAP_region { last block HEAP }; +} +if (isdefinedsymbol(__use_shmem__)) { + place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} \ No newline at end of file diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_ram_industry.ld b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_ram_industry.ld new file mode 100644 index 000000000000..37688e407fb8 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_ram_industry.ld @@ -0,0 +1,259 @@ +ENTRY(Reset_Handler) + +__use_shmem__ = 1; +__multicore__ = 1; + +m_itcm_start = 0x00000000; +m_itcm_size = 0x00040000; +m_dtcm_start = 0x20000000; +m_dtcm_size = 0x00040000; +m_ocram1_start = 0x20484000; +m_ocram1_size = 0x0007C000; +m_ocram2_start = 0x20500000; +m_ocram2_size = 0x00040000; +m_sdram_start = 0x80000000; +m_sdram_size = 0x01E00000; +m_hyperram_start = 0x04000000; +m_hyperram_size = 0x00600000; +m_flash_start = 0x28000000; +m_flash_size = 0x01000000; + +app_image_offset = 0x0000B000; +vector_table_size = 0x00000400; +m_qacode_start = m_itcm_start + (DEFINED(__ram_vector_table__) ? vector_table_size : 0); +m_qacode_end = m_itcm_start + m_itcm_size - 1; +m_qadata_start = m_dtcm_start; +m_qadata_end = m_dtcm_start + m_dtcm_size - 1; +m_ram_vector_table_start = m_itcm_start; +m_stack_size = DEFINED(__stack_size__) ? __stack_size__ : 0x1000; +m_heap_size = DEFINED(__heap_size__) ? __heap_size__ : 0x10000; +m_code_size = m_itcm_size - vector_table_size; +m_data_size = m_dtcm_size; +m_ncache_size = 0x40000; +m_shmem_size = 0x8000; +m_ram_vector_table_size = 0; +m_interrupts_start = m_itcm_start; +m_interrupts_end = m_interrupts_start + vector_table_size - 1; +m_text_start = m_interrupts_end + 1; +m_text_end = m_text_start + m_code_size - 1; +m_data_start = m_dtcm_start; +m_data_end = m_data_start + m_data_size - 1; +m_ncache_start = m_ocram1_start + m_ocram1_size - m_ncache_size; +m_ncache_end = m_ncache_start + m_ncache_size - 1 - (DEFINED(__heap_noncacheable__) ? m_heap_size : 0); +m_heap_start = DEFINED(__heap_noncacheable__) ? m_ncache_end + 1 : m_ocram1_start; +m_heap_end = m_heap_start + m_heap_size - 1; +m_ocram2_data_start = 0x20520000; +m_ocram2_data_size = 0x18000; +m_ocram2_data_end = m_ocram2_data_start + m_ocram2_data_size - 1; +m_rpmsg_sh_mem_start = m_ocram2_start + m_ocram2_size - m_shmem_size; +m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; + +__VECTOR_TABLE = m_interrupts_start; +__VECTOR_RAM = m_ram_vector_table_start; +__RAM_VECTOR_TABLE_SIZE_BYTES = m_ram_vector_table_size; +__NCACHE_REGION_START = m_ncache_start; +__NCACHE_REGION_SIZE = m_ncache_size; +__OCRAM2_DATA_START = m_ocram2_data_start; +__OCRAM2_DATA_SIZE = m_ocram2_data_size; +__RPMSG_SH_MEM_START = DEFINED(__use_shmem__) ? m_rpmsg_sh_mem_start : 0; +__RPMSG_SH_MEM_SIZE = DEFINED(__use_shmem__) ? m_shmem_size : 0; + +ASSERT(m_heap_size > 0, "heap size must be positive") +ASSERT(m_heap_end < (DEFINED(__heap_noncacheable__) ? m_ncache_start + m_ncache_size : m_ncache_start), "heap exceeds OCRAM1 allocation") + +MEMORY +{ + m_interrupts_ram (RX) : ORIGIN = m_ram_vector_table_start, LENGTH = __RAM_VECTOR_TABLE_SIZE_BYTES + m_interrupts (RX) : ORIGIN = m_interrupts_start, LENGTH = vector_table_size + m_text (RX) : ORIGIN = m_text_start, LENGTH = m_code_size + m_data (RW) : ORIGIN = m_data_start, LENGTH = m_data_size + m_ncache (RW) : ORIGIN = m_ncache_start, LENGTH = m_ncache_end - m_ncache_start + 1 + m_heap (RW) : ORIGIN = m_heap_start, LENGTH = m_heap_size + m_qacode (RX) : ORIGIN = m_qacode_start, LENGTH = m_qacode_end - m_qacode_start + 1 + m_qadata (RW) : ORIGIN = m_qadata_start, LENGTH = m_qadata_end - m_qadata_start + 1 + m_ocram2_data (RW) : ORIGIN = m_ocram2_data_start, LENGTH = m_ocram2_data_size + m_rpmsg (RW) : ORIGIN = m_rpmsg_sh_mem_start, LENGTH = m_shmem_size +} + +SECTIONS +{ + .interrupts : + { + . = ALIGN(4); + __Vectors = .; + KEEP(*(.isr_vector)) + . = ALIGN(4); + } > m_interrupts + + .interrupts_ram : + { + . = ALIGN(4); + . += __RAM_VECTOR_TABLE_SIZE_BYTES; + . = ALIGN(4); + } > m_interrupts_ram + + .text : + { + . = ALIGN(4); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + *(CodeQuickAccess) + KEEP(*(.init)) + KEEP(*(.fini)) + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + } > m_text + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > m_text + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + .ctors : + { + __CTOR_LIST__ = .; + KEEP(*crtbegin.o(.ctors)) + KEEP(*crtbegin?.o(.ctors)) + KEEP(*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + __CTOR_END__ = .; + } > m_text + .dtors : + { + __DTOR_LIST__ = .; + KEEP(*crtbegin.o(.dtors)) + KEEP(*crtbegin?.o(.dtors)) + KEEP(*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + __DTOR_END__ = .; + } > m_text + .preinit_array : + { + PROVIDE_HIDDEN(__preinit_array_start = .); + KEEP(*(.preinit_array*)) + PROVIDE_HIDDEN(__preinit_array_end = .); + } > m_text + .init_array : + { + PROVIDE_HIDDEN(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array*)) + PROVIDE_HIDDEN(__init_array_end = .); + } > m_text + .fini_array : + { + PROVIDE_HIDDEN(__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array*)) + PROVIDE_HIDDEN(__fini_array_end = .); + } > m_text + + __etext = .; + __data_flash_start = .; + .data : AT(__data_flash_start) + { + . = ALIGN(4); + __data_start__ = .; + *(.data) + *(.data*) + *(DataQuickAccess) + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; + } > m_data + + __ram_function_flash_start = __data_flash_start + (__data_end__ - __data_start__); + .ram_function : AT(__ram_function_flash_start) + { + . = ALIGN(32); + __ram_function_start__ = .; + . = ALIGN(128); + __ram_function_end__ = .; + } > m_qacode + + __noncache_data_flash_start = __ram_function_flash_start + (__ram_function_end__ - __ram_function_start__); + .ncache.init : AT(__noncache_data_flash_start) + { + . = ALIGN(4); + __noncache_data_start__ = .; + *(NonCacheable.init) + . = ALIGN(4); + __noncache_data_end__ = .; + } > m_ncache + .ncache : + { + . = ALIGN(4); + __noncache_bss_start__ = .; + *(NonCacheable) + . = ALIGN(4); + __noncache_bss_end__ = .; + } > m_ncache + + __qadata_flash_start = __noncache_data_flash_start + (__noncache_data_end__ - __noncache_data_start__); + .qadata : AT(__qadata_flash_start) + { + . = ALIGN(4); + __qadata_start__ = .; + . = ALIGN(4); + __qadata_end__ = .; + } > m_qadata + text_data_end = __qadata_flash_start + (__qadata_end__ - __qadata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(text_data_end < text_end, "region m_text overflowed with text and data") + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > m_data + .ocram2_data (NOLOAD) : + { + . = ALIGN(8); + . += m_ocram2_data_size; + } > m_ocram2_data + .rpmsg : { *(.noinit.$rpmsg_sh_mem) } > m_rpmsg + .heap : + { + . = ALIGN(8); + __HeapBase = .; + end = .; + . += m_heap_size; + __HeapLimit = .; + } > m_heap + .stack : + { + . = ALIGN(8); + __StackStart = .; + . += m_stack_size; + } > m_data + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - m_stack_size; + PROVIDE(__stack = __StackTop); + PROVIDE(__stack_size = m_stack_size); + ASSERT(__StackLimit >= __StackStart, "region m_data overflowed with stack and heap") + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_ram_industry.scf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_ram_industry.scf new file mode 100644 index 000000000000..210817ff1564 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/MIMXRT1189xxxxx_cm7_ram_industry.scf @@ -0,0 +1,117 @@ +#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c + +#define m_itcm_start 0x00000000 +#define m_itcm_size 0x00040000 +#define m_dtcm_start 0x20000000 +#define m_dtcm_size 0x00040000 +#define m_ocram1_start 0x20484000 +#define m_ocram1_size 0x0007C000 +#define m_ocram2_start 0x20500000 +#define m_ocram2_size 0x00040000 +#define m_sdram_start 0x80000000 +#define m_sdram_size 0x01E00000 +#define m_hyperram_start 0x04000000 +#define m_hyperram_size 0x00600000 +#define m_flash_start 0x28000000 +#define m_flash_size 0x01000000 +#define app_image_offset 0x0000B000 +#define vector_table_size 0x400 +#define m_ram_vector_table_start m_itcm_start + +#if defined(__stack_size__) +#define stack_size __stack_size__ +#else +#define stack_size 0x1000 +#endif +#if defined(__heap_size__) +#define heap_size __heap_size__ +#else +#define heap_size 0x10000 +#endif + +#define m_ram_vector_table_size 0 +#define m_qacode_start m_itcm_start + m_ram_vector_table_size +#define m_qadata_start m_dtcm_start +#define m_qacode_size 0 +#define m_qadata_size 0 +#define m_text_size m_itcm_size +#define m_data_size m_dtcm_size +#define m_text_start m_itcm_start +#define m_interrupts_start m_text_start +#define m_data_start m_dtcm_start +#define m_ncache_size 0x40000 +#define m_ncache_start m_ocram1_start + m_ocram1_size - m_ncache_size +#define m_heap_start m_ocram1_start +#define m_ocram2_data_start 0x20520000 +#define m_ocram2_data_size 0x18000 +#define m_shmem_size 0x8000 +#define m_shmem_start m_ocram2_start + m_ocram2_size - m_shmem_size + +#if !defined(__heap_noncacheable__) && (heap_size > (m_ncache_start - m_heap_start)) +#error Heap exceeds the cacheable OCRAM1 region +#endif +#if defined(__heap_noncacheable__) && (heap_size > m_ncache_size) +#error Heap exceeds the non-cacheable OCRAM1 region +#endif + +LR_m_text m_text_start m_text_size +{ + VECTOR_ROM m_interrupts_start FIXED vector_table_size + { + * (.isr_vector,+FIRST) + } + VECTOR_RAM m_ram_vector_table_start EMPTY m_ram_vector_table_size + { + } + ER_m_text m_text_start + vector_table_size FIXED m_text_size - vector_table_size + { + * (InRoot$$Sections) + .ANY (+RO) + .ANY (CodeQuickAccess) + } + ER_m_QuickAccessCode m_qacode_start EMPTY m_qacode_size + { + } + ER_m_QuickAccessData m_qadata_start EMPTY m_qadata_size + { + } + RW_m_data m_data_start m_data_size-stack_size + { + .ANY (+RW +ZI) + .ANY (DataQuickAccess) + } + RW_m_ncache m_ncache_start m_ncache_size + { + .ANY (NonCacheable.init) + .ANY (.bss.NonCacheable) + } +#if defined(__heap_noncacheable__) + ARM_LIB_HEAP +0 ALIGN 0x100 EMPTY heap_size + { + } + ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= (m_ncache_start + m_ncache_size)) +#endif + RW_m_ncache_aux m_ncache_start + m_ncache_size EMPTY 0 + { + } + OCRAM2_DATA m_ocram2_data_start EMPTY m_ocram2_data_size + { + } +#if defined(__use_shmem__) + RPMSG_SH_MEM m_shmem_start m_shmem_size + { + .ANY (rpmsg_sh_mem_section) + } + RPMSG_SH_MEM_aux m_shmem_start + m_shmem_size EMPTY 0 + { + } +#endif +#if !defined(__heap_noncacheable__) + ARM_LIB_HEAP m_heap_start EMPTY heap_size + { + } +#endif + ARM_LIB_STACK m_data_start+m_data_size EMPTY -stack_size + { + } +} \ No newline at end of file diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/readme.md b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/readme.md new file mode 100644 index 000000000000..9badc9e155c1 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/readme.md @@ -0,0 +1,79 @@ +# CM7 Memory Layout + +[English version](readme_en.md) + +本目录提供六种 CM7 内存布局，每种都有 GCC `.ld`、Keil `.scf` 和 IAR `.icf` 文件。 +下表地址为 CM7 视角，结束地址包含在区域内；KB/MB 按 1024/1048576 字节计算，容量不代表实际占用。 + +## 1. 当前内存布局 + +| 内存 | 起始地址 | 结束地址 | 容量 | 用途 | +| --- | --- | --- | --- | --- | +| ITCM | `0x00000000` | `0x0003FFFF` | 256KB | RAM 类 target 的向量和代码；XIP 类 target 的快速代码 | +| DTCM | `0x20000000` | `0x2003FFFF` | 256KB | 普通数据和主栈，或快速数据 | +| OCRAM1 | `0x20484000` | `0x204FFFFF` | 496KB | Heap 和 non-cacheable 缓冲区；避开 TRDC 禁止访问的前 16KB | +| OCRAM2 | `0x20500000` | `0x2053FFFF` | 256KB | 双核共享内存，工业布局另划分独占区域 | +| HyperRAM | `0x04000000` | `0x045FFFFF` | 6MB | HyperRAM 类 target 的普通数据和主栈；另预留 2MB 给 CM33 | +| FlexSPI NOR | `0x28800000` | `0x28FFFFFF` | 8MB | XIP 类 target 的向量、代码及数据初值 | + +RAM 类向量占 ITCM 首部 1KB，代码从 `0x00000400` 开始；其初始化数据副本也占用 ITCM 镜像空间。 +XIP 类向量占 Flash 首部 1KB，普通代码从 `0x28800400` 开始。 +HyperRAM 类的快速数据仍在 DTCM，Heap 仍在 OCRAM1。当前六种布局的主要内容均不放入 SDRAM。 + +### 普通 OCRAM 布局 + +适用于 `RAM`、`HYPERRAM`、`FLEXSPI_NOR`、`FLEXSPI_NOR_HYPERRAM`。 +以下按双核配置（定义 `__multicore__`）且使用 cacheable Heap 说明，共享区需启用 `__use_shmem__`。 + +| 区域 | 起始地址 | 结束地址 | 容量 | +| --- | --- | --- | --- | +| OCRAM1 低地址部分，未分配给本 CM7 布局 | `0x20484000` | `0x204BFFFF` | 240KB | +| CM7 Heap 可用窗口 | `0x204C0000` | `0x204DFFFF` | 128KB | +| CM7 non-cacheable 缓冲区 | `0x204E0000` | `0x204FFFFF` | 128KB | +| 双核共享 OCRAM2 | `0x20500000` | `0x2053FFFF` | 256KB | + +未定义 `__multicore__` 时，Heap 窗口改为 OCRAM1 低地址 240KB，non-cacheable 窗口改为高地址 256KB。 + +### 工业以太网 OCRAM 布局 + +适用于 `RAM_INDUSTRY`、`FLEXSPI_NOR_INDUSTRY`，以下按 cacheable Heap 说明。 + +| 区域 | 起始地址 | 结束地址 | 容量 | +| --- | --- | --- | --- | +| CM7 Heap 可用窗口 | `0x20484000` | `0x204BFFFF` | 240KB | +| CM7 non-cacheable 缓冲区 | `0x204C0000` | `0x204FFFFF` | 256KB | +| CM33 独占 OCRAM2 | `0x20500000` | `0x2051FFFF` | 128KB | +| CM7 独占额外 OCRAM2 | `0x20520000` | `0x20537FFF` | 96KB | +| 双核共享 OCRAM2 | `0x20538000` | `0x2053FFFF` | 32KB | + +工业布局将更多 OCRAM1 留给 CM7，并把 OCRAM2 分成 CM33 128KB、CM7 96KB、共享 32KB。 +双核必须使用匹配的分区；额外 96KB 不会自动加入系统 Heap。 + +## 2. 各 Target 的差异 + +| Target 类型 | 向量/普通代码 | 普通数据/主栈 | OCRAM 布局 | 默认 Heap | 默认主栈 | +| --- | --- | --- | --- | --- | --- | +| `RAM` | ITCM | DTCM | 普通 | 32KB | 4KB | +| `RAM_INDUSTRY` | ITCM | DTCM | 工业 | 64KB | 4KB | +| `HYPERRAM` | ITCM | HyperRAM | 普通 | 32KB | 4KB | +| `FLEXSPI_NOR` | Flash XIP | DTCM | 普通 | 32KB | 4KB | +| `FLEXSPI_NOR_HYPERRAM` | Flash XIP | HyperRAM | 普通 | 32KB | 4KB | +| `FLEXSPI_NOR_INDUSTRY` | Flash XIP | DTCM | 工业 | 64KB | 4KB | + +GCC、Keil、IAR 的默认 Heap/主栈容量已一致，但具体 Heap 放置地址可能不同。 +Heap 窗口容量不等于默认分配大小，主栈也不是各 RT-Thread 线程的独立栈。 +以上为默认值；工程可覆盖堆栈大小或将 Heap 改为 non-cacheable。 + +## 3. 应用范围 + +| Target 类型 | 适用场景 | +| --- | --- | +| `RAM` | 内部 RAM 调试、小型实时应用，不依赖外部 RAM | +| `RAM_INDUSTRY` | 内部 RAM 运行的工业以太网/EtherCAT 双核开发，需要更大的内部缓冲区 | +| `HYPERRAM` | 代码在 ITCM 运行，数据量较大的采集、图像处理或大缓冲区应用 | +| `FLEXSPI_NOR` | 常规 Flash XIP 应用，代码较大但普通数据可放入内部 DTCM | +| `FLEXSPI_NOR_HYPERRAM` | 同时需要较大代码空间和数据空间的图形、通信或数据处理应用 | +| `FLEXSPI_NOR_INDUSTRY` | Flash XIP 的工业以太网/EtherCAT 双核应用，需要 CM7 独占 OCRAM2 和更多 non-cacheable 缓冲区 | + +RAM 类镜像需要调试器或启动流程装载；HyperRAM 必须在数据和主栈使用前可访问。 +共享通信需启用共享区，工业双核分区需与 CM33 一致。链接布局只决定存放位置，不代替外设和通信初始化。 \ No newline at end of file diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/readme_en.md b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/readme_en.md new file mode 100644 index 000000000000..fb00b04997ee --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/readme_en.md @@ -0,0 +1,79 @@ +# CM7 Memory Layout + +[Chinese version](readme.md) + +This directory provides six CM7 memory layouts, each with GCC `.ld`, Keil `.scf`, and IAR `.icf` files. +Addresses are from the CM7 perspective and table end addresses are inclusive. KB/MB mean 1024/1048576 bytes; capacities are not actual usage. + +## 1. Current Memory Layout + +| Memory | Start | End | Capacity | Purpose | +| --- | --- | --- | --- | --- | +| ITCM | `0x00000000` | `0x0003FFFF` | 256KB | Vectors and code for RAM targets; quick-access code for XIP targets | +| DTCM | `0x20000000` | `0x2003FFFF` | 256KB | Ordinary data and main stack, or quick-access data | +| OCRAM1 | `0x20484000` | `0x204FFFFF` | 496KB | Heap and non-cacheable buffers; excludes the first 16KB blocked by TRDC | +| OCRAM2 | `0x20500000` | `0x2053FFFF` | 256KB | Multicore shared memory; industry layouts also reserve exclusive areas | +| HyperRAM | `0x04000000` | `0x045FFFFF` | 6MB | Ordinary data and main stack for HyperRAM targets; another 2MB is reserved for CM33 | +| FlexSPI NOR | `0x28800000` | `0x28FFFFFF` | 8MB | Vectors, code, and data initial values for XIP targets | + +RAM targets reserve the first 1KB of ITCM for vectors, with code starting at `0x00000400`. Initialization copies also consume ITCM image space. +XIP targets reserve the first 1KB of Flash for vectors, with ordinary code starting at `0x28800400`. +HyperRAM targets keep quick-access data in DTCM and the heap in OCRAM1. None of these six layouts places its main contents in SDRAM. + +### Standard OCRAM Layout + +Applies to `RAM`, `HYPERRAM`, `FLEXSPI_NOR`, and `FLEXSPI_NOR_HYPERRAM`. +The table assumes multicore configuration (`__multicore__` defined) and a cacheable heap. Shared memory requires `__use_shmem__` to be enabled. + +| Region | Start | End | Capacity | +| --- | --- | --- | --- | +| Lower OCRAM1, not assigned to this CM7 layout | `0x20484000` | `0x204BFFFF` | 240KB | +| CM7 available heap window | `0x204C0000` | `0x204DFFFF` | 128KB | +| CM7 non-cacheable buffers | `0x204E0000` | `0x204FFFFF` | 128KB | +| Multicore shared OCRAM2 | `0x20500000` | `0x2053FFFF` | 256KB | + +Without `__multicore__`, the heap window moves to the lower 240KB of OCRAM1, and the non-cacheable window becomes the upper 256KB. + +### Industrial Ethernet OCRAM Layout + +Applies to `RAM_INDUSTRY` and `FLEXSPI_NOR_INDUSTRY`. The table assumes a cacheable heap. + +| Region | Start | End | Capacity | +| --- | --- | --- | --- | +| CM7 available heap window | `0x20484000` | `0x204BFFFF` | 240KB | +| CM7 non-cacheable buffers | `0x204C0000` | `0x204FFFFF` | 256KB | +| CM33-exclusive OCRAM2 | `0x20500000` | `0x2051FFFF` | 128KB | +| CM7-exclusive additional OCRAM2 | `0x20520000` | `0x20537FFF` | 96KB | +| Multicore shared OCRAM2 | `0x20538000` | `0x2053FFFF` | 32KB | + +Industry layouts assign more OCRAM1 to CM7 and split OCRAM2 into 128KB for CM33, 96KB for CM7, and 32KB shared. +Both cores must use matching partitions. The additional 96KB is not automatically added to the system heap. + +## 2. Target Differences + +| Target type | Vectors/ordinary code | Ordinary data/main stack | OCRAM layout | Default heap | Default main stack | +| --- | --- | --- | --- | --- | --- | +| `RAM` | ITCM | DTCM | Standard | 32KB | 4KB | +| `RAM_INDUSTRY` | ITCM | DTCM | Industry | 64KB | 4KB | +| `HYPERRAM` | ITCM | HyperRAM | Standard | 32KB | 4KB | +| `FLEXSPI_NOR` | Flash XIP | DTCM | Standard | 32KB | 4KB | +| `FLEXSPI_NOR_HYPERRAM` | Flash XIP | HyperRAM | Standard | 32KB | 4KB | +| `FLEXSPI_NOR_INDUSTRY` | Flash XIP | DTCM | Industry | 64KB | 4KB | + +GCC, Keil, and IAR now use the same default heap/main-stack capacities, although actual heap placement can differ. +Heap window capacity is not the default allocated heap size, and the main stack is not each RT-Thread thread's individual stack. +These are defaults; projects can override sizes or select a non-cacheable heap. + +## 3. Application Scope + +| Target type | Suitable applications | +| --- | --- | +| `RAM` | Internal-RAM debugging and small real-time applications without external RAM | +| `RAM_INDUSTRY` | Internal-RAM industrial Ethernet/EtherCAT multicore development requiring larger internal buffers | +| `HYPERRAM` | ITCM code execution with data-intensive acquisition, image processing, or large buffers | +| `FLEXSPI_NOR` | Conventional Flash XIP applications with larger code and ordinary data that fits in internal DTCM | +| `FLEXSPI_NOR_HYPERRAM` | Graphics, communications, or data-processing applications needing both larger code and data spaces | +| `FLEXSPI_NOR_INDUSTRY` | Flash XIP industrial Ethernet/EtherCAT multicore applications requiring CM7-exclusive OCRAM2 and more non-cacheable buffers | + +RAM images require loading by a debugger or boot flow. HyperRAM must be accessible before ordinary data and the main stack are used. +Shared communication requires shared memory to be enabled, and industry partitions must match CM33. Memory layouts determine placement, not peripheral or communication initialization. \ No newline at end of file diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.h index fe014c45134b..2855d6f9ac8d 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.h +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.h @@ -106,7 +106,7 @@ #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart12" #define RT_USING_CONSOLE_OUTPUT_CTL -#define RT_VER_NUM 0x50300 +#define RT_VER_NUM 0x50400 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define RT_USING_CACHE @@ -256,6 +256,9 @@ /* LVGL: powerful and easy-to-use embedded GUI library */ + +/* GD32EmbeddedUI demos require LVGL v8.3.11 */ + /* end of LVGL: powerful and easy-to-use embedded GUI library */ /* u8g2: a monochrome graphic library */ @@ -302,6 +305,10 @@ /* end of Kendryte SDK */ +/* MM32 HAL & SDK Drivers */ + +/* end of MM32 HAL & SDK Drivers */ + /* WCH HAL & SDK Drivers */ /* end of WCH HAL & SDK Drivers */ @@ -332,9 +339,21 @@ /* end of HPMicro SDK */ +/* FM33 Drivers */ + +/* end of FM33 Drivers */ + /* FT32 HAL & SDK Drivers */ /* end of FT32 HAL & SDK Drivers */ + +/* NOVOSNS Drivers */ + +/* end of NOVOSNS Drivers */ + +/* N32 Drivers */ + +/* end of N32 Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.py b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.py index 5cd0142118f8..efab680241ab 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.py +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.py @@ -29,11 +29,11 @@ if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') -BUILD = 'debug' -# BUILD = 'release' +# BUILD = 'debug' +BUILD = 'release' # Read linker script selection from rtconfig.h (set by Kconfig BSP_LINKER_SCRIPT_* choice). -# Supported types: RAM, HYPERRAM, FLEXSPI_NOR, FLEXSPI_NOR_HYPERRAM +# Supported types: RAM, RAM_INDUSTRY, HYPERRAM, FLEXSPI_NOR, FLEXSPI_NOR_HYPERRAM, FLEXSPI_NOR_INDUSTRY # Default to RAM when no match is found. _LINKER_SCRIPT_TYPE = 'RAM' _rtconfig_h = os.path.join(os.path.dirname(__file__), 'rtconfig.h') @@ -47,12 +47,18 @@ if _s.startswith('#define BSP_LINKER_SCRIPT_FLEXSPI_NOR_HYPERRAM'): _LINKER_SCRIPT_TYPE = 'FLEXSPI_NOR_HYPERRAM' break + if _s.startswith('#define BSP_LINKER_SCRIPT_FLEXSPI_NOR_INDUSTRY'): + _LINKER_SCRIPT_TYPE = 'FLEXSPI_NOR_INDUSTRY' + break if _s.startswith('#define BSP_LINKER_SCRIPT_FLEXSPI_NOR'): _LINKER_SCRIPT_TYPE = 'FLEXSPI_NOR' break if _s.startswith('#define BSP_LINKER_SCRIPT_HYPERRAM'): _LINKER_SCRIPT_TYPE = 'HYPERRAM' break + if _s.startswith('#define BSP_LINKER_SCRIPT_RAM_INDUSTRY'): + _LINKER_SCRIPT_TYPE = 'RAM_INDUSTRY' + break if _s.startswith('#define BSP_LINKER_SCRIPT_RAM'): _LINKER_SCRIPT_TYPE = 'RAM' break @@ -60,9 +66,11 @@ # Base filename (without extension) for the selected linker script. _LINKER_SCRIPT_BASE = { 'RAM': 'MIMXRT1189xxxxx_cm7_ram', + 'RAM_INDUSTRY': 'MIMXRT1189xxxxx_cm7_ram_industry', 'HYPERRAM': 'MIMXRT1189xxxxx_cm7_hyperram', 'FLEXSPI_NOR': 'MIMXRT1189xxxxx_cm7_flexspi_nor', 'FLEXSPI_NOR_HYPERRAM': 'MIMXRT1189xxxxx_cm7_flexspi_nor_hyperram', + 'FLEXSPI_NOR_INDUSTRY': 'MIMXRT1189xxxxx_cm7_flexspi_nor_industry', }[_LINKER_SCRIPT_TYPE] @@ -245,9 +253,11 @@ # Map from linker script type to the matching Keil target name. _LINKER_SCRIPT_TO_KEIL_TARGET = { 'RAM': 'rtthread_ram', + 'RAM_INDUSTRY': 'rtthread_ram_industry', 'HYPERRAM': 'rtthread_hyperram', 'FLEXSPI_NOR': 'rtthread_flexspi_nor', 'FLEXSPI_NOR_HYPERRAM': 'rtthread_flexspi_nor_hyperram', + 'FLEXSPI_NOR_INDUSTRY': 'rtthread_flexspi_nor_industry', } def update_keil_active_target(uvoptx_path='project.uvoptx'): @@ -262,6 +272,10 @@ def update_keil_active_target(uvoptx_path='project.uvoptx'): tree = etree.parse(uvoptx_path) root = tree.getroot() + if not any(tgt.findtext('TargetName') == active for tgt in tree.findall('Target')): + print('Keil target not found: ' + active + '; active target unchanged') + return + for tgt in tree.findall('Target'): tname = tgt.find('TargetName') is_current = tgt.find('TargetOption/OPTFL/IsCurrentTarget') diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewd b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewd index 820c6102c6e8..672e0eca0066 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewd +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewd @@ -4920,6 +4920,1645 @@ 0 + + rtthread_flexspi_nor_industry + + ARM + + 1 + + C-SPY + 2 + + 33 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + E2_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + GPLINK_ID + 2 + + 0 + 1 + 1 + + + + + + + IJET_ID + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 1 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 1 + + + + + + + + STLINK_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\Azure\AzureArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9a.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + rtthread_flexspi_nor_hyperram @@ -6561,4 +8200,1644 @@ + + rtthread_ram_industry + + ARM + + 1 + + C-SPY + 2 + + 33 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + E2_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + GPLINK_ID + 2 + + 0 + 1 + 1 + + + + + + + IJET_ID + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 1 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 1 + + + + + + + + STLINK_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\Azure\AzureArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9a.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewp b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewp index 4227328af4f0..82c3076f547b 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewp +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewp @@ -3297,6 +3297,1104 @@ 2 + + rtthread_flexspi_nor_industry + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + rtthread_flexspi_nor_hyperram @@ -4402,4 +5500,1103 @@ true + + rtthread_ram_industry + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.uvoptx b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.uvoptx index 55a3a16d0e3b..92b530b01294 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.uvoptx +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.uvoptx @@ -75,7 +75,7 @@ 0 0 - 1 + 0 8 @@ -516,6 +516,171 @@ + + rtthread_flexspi_nor_industry + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 0 + + 8 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + .\evkmimxrt1180_flexspi_nor_cm7.ini + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U603001820 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(5BA02477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD30500000 -FC8000 -FN1 -FF0MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLMIMXRT1180 CM7 FLEXSPI -FS028000000 -FL01000000 -FP0($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN2 -FC20000 -FD20000000 -FF0MIMXRT1180_EVK_FSPI1_QSPI_CM33 -FF1MIMXRT1180_EVK_FSPI1_QSPI_CM7 -FL01000000 -FL11000000 -FS028000000 -FS128000000 -FP0($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM33.FLM) -FP1($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLM) + + + 0 + CMSIS_AGDI + UL2CM3(-S0 -C0 -P0 ) -FN2 -FC20000 -FD20000000 -FF0MIMXRT1180_EVK_FSPI1_QSPI_CM33 -FF1MIMXRT1180_EVK_FSPI1_QSPI_CM7 -FL01000000 -FL11000000 -FS028000000 -FS128000000 -FP0($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM33.FLM) -FP1($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + + rtthread_flexspi_nor_hyperram 0x4 @@ -681,4 +846,169 @@ + + rtthread_ram_industry + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\ram_industry\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 8 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + .\evkmimxrt1180_ram_cm7.ini + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U603001820 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(5BA02477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD30500000 -FC8000 -FN1 -FF0MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLMIMXRT1180 CM7 FLEXSPI -FS028000000 -FL01000000 -FP0($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN2 -FC20000 -FD20000000 -FF0MIMXRT1180_EVK_FSPI1_QSPI_CM33 -FF1MIMXRT1180_EVK_FSPI1_QSPI_CM7 -FL01000000 -FL11000000 -FS028000000 -FS128000000 -FP0($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM33.FLM) -FP1($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLM) + + + 0 + CMSIS_AGDI + UL2CM3(-S0 -C0 -P0 ) -FN2 -FC20000 -FD20000000 -FF0MIMXRT1180_EVK_FSPI1_QSPI_CM33 -FF1MIMXRT1180_EVK_FSPI1_QSPI_CM7 -FL01000000 -FL11000000 -FS028000000 -FS128000000 -FP0($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM33.FLM) -FP1($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.uvprojx b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.uvprojx index 78acfd77ca4d..2271da9c970e 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.uvprojx +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.uvprojx @@ -1132,7 +1132,7 @@ - rtthread_flexspi_nor_hyperram + rtthread_flexspi_nor_industry 0x4 ARM-ADS 6220000::V6.22::ARMCLANG @@ -1496,7 +1496,7 @@ 0x00000000 0x10000000 - .\board\linker_scripts\MIMXRT1189xxxxx_cm7_flexspi_nor_hyperram.scf + .\board\linker_scripts\MIMXRT1189xxxxx_cm7_flexspi_nor_industry.scf --legacyalign @@ -1506,6 +1506,756 @@ + + rtthread_flexspi_nor_hyperram + 0x4 + ARM-ADS + 6220000::V6.22::ARMCLANG + 1 + + + MIMXRT1189CVM8C:cm7 + NXP + NXP.MIMXRT1189_DFP.25.06.00 + https://mcuxpresso.nxp.com/cmsis_pack/repo/ + IRAM(0x20484000,0x07c000) IRAM2(0x20500000,0x040000) IROM(0x00000000,0x028000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC20000 -FN2 -FF0MIMXRT1180_EVK_FSPI1_QSPI_CM33 -FS028000000 -FL01000000 -FF1MIMXRT1180_EVK_FSPI1_QSPI_CM7 -FS128000000 -FL11000000 -FP0($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM33.FLM) -FP1($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLM)) + 0 + $$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\fsl_device_registers.h + + + + + + + + + + $$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\MIMXRT1189_cm7.xml + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 1 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 3 + 0 + 0 + 0 + 1 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20484000 + 0x7c000 + + + 1 + 0x0 + 0x28000 + + + 1 + 0x1ffe0000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x28000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20484000 + 0x7c000 + + + 0 + 0x20500000 + 0x40000 + + + + + + 1 + 5 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + -xc -std=gnu99 -mimplicit-float + RELOC_VECTOR + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + -x assembler-with-cpp + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x10000000 + + .\board\linker_scripts\MIMXRT1189xxxxx_cm7_flexspi_nor_hyperram.scf + + + --legacyalign + + 6439,6314 + + + + + + rtthread_ram_industry + 0x4 + ARM-ADS + 6220000::V6.22::ARMCLANG + 1 + + + MIMXRT1189CVM8C:cm7 + NXP + NXP.MIMXRT1189_DFP.25.06.00 + https://mcuxpresso.nxp.com/cmsis_pack/repo/ + IRAM(0x20484000,0x07c000) IRAM2(0x20520000,0x018000) IROM(0x00000000,0x040000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC20000 -FN2 -FF0MIMXRT1180_EVK_FSPI1_QSPI_CM33 -FS028000000 -FL01000000 -FF1MIMXRT1180_EVK_FSPI1_QSPI_CM7 -FS128000000 -FL11000000 -FP0($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM33.FLM) -FP1($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLM)) + 0 + $$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\fsl_device_registers.h + + + + + + + + + + $$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\MIMXRT1189_cm7.xml + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\ram_industry\Obj\ + rtthread + 1 + 0 + 1 + 1 + 1 + .\build\keil\ram_industry\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 0 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 3 + 0 + 0 + 0 + 1 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20484000 + 0x7c000 + + + 1 + 0x0 + 0x40000 + + + 1 + 0x1ffe0000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20484000 + 0x7c000 + + + 0 + 0x20520000 + 0x18000 + + + + + + 1 + 5 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + -xc -std=gnu99 -mimplicit-float + RELOC_VECTOR + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + -x assembler-with-cpp + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\board\linker_scripts\MIMXRT1189xxxxx_cm7_ram_industry.scf + + + --legacyalign --predefine="-D__use_shmem__=1 -D__multicore__=1" + + 6439,6314 + + + + diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_flexspi.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_flexspi.c index 8e1b3b997446..e9b2d3d1b866 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_flexspi.c +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_flexspi.c @@ -70,7 +70,7 @@ static flexspi_device_config_t deviceconfig = { .AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle, .AHBWriteWaitInterval = 0, }; -const uint32_t customLUT[CUSTOM_LUT_LENGTH] = { +uint32_t customLUT[CUSTOM_LUT_LENGTH] = { /* 8bit mode */ [4 * ARD_SEQ_INDEX] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_8PAD, 0), @@ -98,7 +98,7 @@ static flexspi_device_config_t deviceconfig = { .AHBWriteWaitInterval = 0, }; -const uint32_t customLUT[CUSTOM_LUT_LENGTH] = { +uint32_t customLUT[CUSTOM_LUT_LENGTH] = { #ifndef BSP_USING_OSPI_FLASH /* Normal read mode - SDR */ [4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL] =