From 81ef969d33a91b33cccba3ce2ffcd477b87f8292 Mon Sep 17 00:00:00 2001 From: kudomcho Date: Thu, 29 Oct 2026 14:04:35 -0400 Subject: [PATCH] Add ROCm-specific fp32 thresholds for test_gemv_4bit ROCm/HIP 4-bit GEMV on gfx1200 produces slightly higher fp32 numerical error than CUDA due to different FMA reduction ordering. Add dedicated fp32 thresholds for ROCm, following the same override pattern used for CPU AVX512BF16. Verified on gfx1200 (RX 9060 XT) with all 192 test_gemv_4bit cases passing. Co-Authored-By: Claude --- tests/test_functional.py | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/tests/test_functional.py b/tests/test_functional.py index e4cd6a128..3aca66641 100644 --- a/tests/test_functional.py +++ b/tests/test_functional.py @@ -916,6 +916,14 @@ def test_gemv_4bit(self, device, dim, dtype, storage_type, double_quant, kind): }, }[dim_key] + # ROCm/HIP 4-bit GEMV has slightly different FMA reduction order, producing + # higher fp32 numerical error than CUDA. Only fp32 is affected. + if torch.version.hip and dtype == torch.float32 and not cpu_bf16_cast: + thresholds = { + "le512": {"err1": (4e-8, 4e-9), "relerr1": (1.6e-6, 2.4e-6), "maxerr1": (1.2e-7, 4e-8)}, + "gt512": {"err1": (2.5e-8, 4e-9), "relerr1": (1e-6, 3.2e-7), "maxerr1": (3.5e-7, 5e-8)}, + }[dim_key] + for metric_name, metric_val in [("err1", err1), ("relerr1", relerr1), ("maxerr1", maxerr1)]: mean_val, std_val = thresholds[metric_name] limit = mean_val + N_SIGMA * std_val