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ROCm/HIP 4-bit GEMV on gfx1200 produces slightly higher fp32 numerical error than CUDA due to different FMA reduction ordering. Add dedicated fp32 thresholds for ROCm, following the same override pattern used for CPU AVX512BF16. Verified on gfx1200 (RX 9060 XT) with all 192 test_gemv_4bit cases passing. Co-Authored-By: Claude <noreply@anthropic.com>
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Summary
test_gemv_4bitintests/test_functional.pytorch.version.hipTest plan
test_gemv_4bitcases pass on gfx1200 (RX 9060 XT) with ROCm 6.3/6.4 — 0 failures across fp16, bf16, and fp32ruff,ruff format,typos,clang-format, etc.)torch.version.hip, so CUDA path is unchanged)