ROHD (pronounced like "road") is a silicon-proven framework for describing and verifying hardware in the Dart programming language.
For documentation, guides, and more, visit the ROHD Website!
You can also open this repository in a GitHub Codespace to run the example in your browser with a full IDE. This is also an easy way to get started with contributions!
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Full power of the modern Dart language for hardware design and verification
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Can use the excellent pub.dev package manager and all the packages it has to offer
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Develop layers of abstraction within a hardware design, making it more flexible and powerful
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Less verbose than alternatives (fewer lines of code)
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Fewer bugs and lines of code means shorter development schedule
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Enables higher quality development
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Simple and fast build, free of complex build systems and EDA vendor tools
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Excellent, simple, fast unit-testing framework
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Simulate with various abstraction levels of models from architectural, to functional, to cycle-accurate, to RTL levels in the same language and environment
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Simple, free, open source tool stack without any headaches from library dependencies, file ordering, elaboration/analysis options, +defines, etc.
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Use modern IDEs like Visual Studio Code, with excellent static analysis, fast autocomplete, built-in debugger, linting, git integration, extensions, and much more
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Easy IP integration and interfaces; using an IP is as easy as an import. Reduces tedious, redundant, and error prone aspects of integration
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Conversion of modules to human-readable, structurally similar SystemVerilog and SystemC for integration or downstream tool consumption
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Run-time dynamic module port definitions (numbers, names, widths, etc.) and internal module logic, including recursive module contents
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Replaces hacky perl/python scripting for automation with powerful native control of design generation
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The ROHD Framework is a complete design and verification framework:
- Built-in event-based fast simulator with 4-value (0, 1, X, and Z) support and a waveform capture service to .vcd or .fst file format
- Leverage the ROHD Hardware Component Library (ROHD-HCL) with reusable and configurable design and verification components
- Makes validation collateral simpler to develop and debug. The ROHD Verification Framework helps build well-structured testbenches
- Powerful capabilities like the ROHD Schematic Viewer for high-fidelity rendering of ROHD designs as well as ROHD Wave Viewer for viewing simulation waveforms even for complex ROHD structures
- Debug your design with ROHD Live Debugger, an integrated debugger with cross-probing into ROHD source and synthesized RTL output from schematics rendering and waveform display all connected to live RTL simulation
- Support for cosimulation with Verilog modules (via ROHD Cosim) and instantiation of Verilog modules in generated SystemVerilog code
ROHD is not a new language, it is not a hardware description language (HDL), and it is not a version of High-Level Synthesis (HLS). ROHD can be classified as a generator framework, extending a powerful software language into the hardware domain and providing a full suite of tools and capabilities to accelerate hardware design and validation.
You can think of this project as an attempt to replace SystemVerilog and related design systems as the front-end methodology of choice in the industry.
One of ROHD's goals is to help grow an open-source community around reusable hardware designs and verification components.
ROHD is under active development. If you're interested in contributing, have feedback or a question, or found a bug, please see CONTRIBUTING.md.
Copyright (C) 2021-2026 Intel Corporation
SPDX-License-Identifier: BSD-3-Clause